8

INPUT TIMING OF SERIAL DATA

latch

DATA

CLK

LE

read

This logic circuit is controlled by a 3-wire serial bus interface with DATA (12 pin), CLK (13 pin) and LE (14 pin).

On the control setting, Binary-coded serial data is input to DATA pin. This data is read into the shift register at the

rising edge of the CLK signal input to the CLK pin. When the LE signal is at the low level, DATA CLK are received

into the LSI to be latched at the rising edge of the LE signal.

While the LE signal is at the high level, neither DATA nor CLK signals can be received.

the non-data input stage. [Refer to ‘Power-save (pin 11)’ on 12 page]