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AN2478 Datasheet(PDF) 10 Page - STMicroelectronics |
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AN2478 Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 21 page Error detection output test circuit AN2478 10/21 4 Error detection output test circuit During the error detection time, the internal structure of the device allows only an output current test. This is done by comparing the current flowing from the output and the current set by the programming resistor "REXT". If the read current is typically less than 50% of the current set by "REXT", the device marks the output as malfunctioning, and converts the previous data loaded into the shift register from 1 to 0. These results are then transferred by the SDO pin. Table 2 shows an example of the measured error detection threshold for several output current levels, as set by "REXT". To correctly run the output error detection, all signals must be synchronized with the falling edge of the CLK signal. This is necessary to avoid any setup/hold time problems. If this rule cannot be applied due to specific application conditions (data generated by a microcontroller, for example), it is possible to start the OE signal typically at 20 ns of delay after the rise time of the CLK signal. The next two plots show a typical error detection mode problem due to wrong error key (LE/DM1 or OE/DM2). Figure 9. Error detection sequence problem due to LE/DM1 synchronization Table 2. Error threshold test results Vdd (V) Iset (mA) Measured error threshold 52.27 10 5.32 3.3 20 8.38 50 17.91 80 29.06 51.88 10 4.81 520 6.44 50 18.54 80 31.36 Error Detection Problem due to OE signal No detection was Observed |
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