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UPD17P207GF-003 Datasheet(PDF) 5 Page - NEC |
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UPD17P207GF-003 Datasheet(HTML) 5 Page - NEC |
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5 / 32 page  µPD17P207 5 BLOCK DIAGRAM Remark Inside the parenthesis indicates pin names in the PROM programming mode. P1A0 SCK P1A1/SO P1A2/SI P0A0 (D0) P0D0/LED P0D1/TMOUT P0D2 P0D3 REM P1A P0A P0B P0C P0D Timer/ Counter RAM 336 × 4 bits SYSTEM REG. One Time PROM 4096 × 16 bits Program Counter Stack 5 × 12 bits Instruction Decoder VREG VDD CAPH CAPL VLCD0 VLCD1 VLCD2 VLCDC GMD LCD0 LCD1 LCD2 LCD3 LCD4 LCD33 COM3/LCD34 COM2/LCD35 COM1 COM0 CPU Clock Clock Stop CPU Clock VADC ADC0 ADC1 ADC2 ADC3 GNDADC Interrupt Controller LCD Controller RESET WDOUT XOUT XTIN XTOUT Power Supply Circuit ALU Watch Timer Divider Main clock Subclock RF Serial Interface P0A1 (D1) P0A2 (D2) P0A3 (D3) P0B0 (MD0) P0B1 (MD1) P0B2 (MD2) P0B3 (MD3) P0C0 (D4) P0C1 (D5) P0C2 (D6) P0C3 (D7) INT (V ) pp A/D Converter X (CLK) IN Carrier Generator |
Similar Part No. - UPD17P207GF-003 |
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Similar Description - UPD17P207GF-003 |
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