TQM829007

0.6-1.0 GHz ¼ W Digital Variable Gain Amplifier

Datasheet: Rev H 05-02-14

- 8 of 10 -

Disclaimer: Subject to change without notice

© 2014 TriQuint

www.triquint.com

Pin Configuration and Description

LE

DATA

CLK

NC

GND

RFIN

GND

1

2

3

4

5

6

7

21

20

19

18

17

16

15

GND

GND

GND

GND

GND

RFOUT

GND

DSA

AMP1

Backside Pad

GND

S

P

I

DC Biasing

Matching

DC Biasing

AMP2

Pin No.

Label

Description

1

LE

Serial Latch Enable Input. When LE is high, latch is clear and content of SPI control

the attenuator. When LE is low, data in SPI is latched.

2

DATA

Serial data input. The data and clock pins allow the data to be entered serially into

SPI and is independent of Latch state.

3

CLK

Serial clock input.

4, 22

N/C

No connect or open. This pin is not connected in this module

6

RFIN

Input, matched to 50 ohms. Internally DC blocked.

8

VCC_AMP1

Supply Voltage to AMP1. This pin is connected internally to 2 bypass capacitors

(100 pF, 0.1 uF) followed by a 68 nH inductor inside the module.

14

VCC_AMP2

Supply Voltage to AMP2. This pin is connected internally to 2 bypass capacitors

(100 pF, 0.1 uF) followed by a 47 nH inductor inside the module.

16

RFOUT

Output matched to 50 ohms. Internally DC blocked.

28

VCC_SPI

SPI and DSA DC supply. Internal connection to 0.1 uF bypass capacitor.

5, 7, 9-13, 15,17-21, 23-27

GND

RF/DC Ground Connection

Backside Pad

GND

RF/DC Ground Connection

Evaluation Board PCB Information

TriQuint PCB 1080956 Material and Stack-up