Feedback Network Implementation (constant power load, refer to fig. 8b):

Output Divider Upper Resistor

R7:

=

OVP

40

R7 = 1

k

Ω

Output Divider Lower Resistor

R8:

=

2.5

⋅ R7

R8 = 6.289

k

Ω

Parallel Feedback Resistor:

⋅ R7

R12 = 300

k

Ω

Series Feedback Capacitor

C3:

=

10

6

2

⋅ 



1

p

⋅

1

z







C3 = 2.271

nF

Series Feedback Resistor

R11:

=

10

6

2

R11 = 4.672

k

Ω

Control-to-Output Transfer Function (resistive load):

G

(ω) : =

km

4

⋅

⋅

1

1

2

Pole Location:

p :

=

10

6

p = 3.386

Hz

0.1

1

10

100

1 .10

3

50

0

50

100

¦G¦

f

0.1

1

10

100

1 .10

3

100

80

60

40

20

0

/G

f

AN1089 APPLICATION NOTE

9/12