RD151TS502US_15 datasheet(4/9 Pages) RENESAS

Part #	RD151TS502US

Description	PLL clock generator series

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Manufacturer	RENESAS [Renesas Technology Corp]

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RD151TS502US

REJ03D0898-0100 Rev.1.00 Apr 25, 2007

Page 2 of 6

Block Diagram

1/M

1/N

VDD

VSS

IN

OUT

PDWN

Synthesizer

DIV

SEL

DIV2

Rpd = 100 k

Ω

Rpd = 100 k

Ω

Rpd = 100 k

Ω

Rpd = 100 k

Ω

Pin Descriptions

Pin name

No.

Type

Description

VDD

1,2

Power

Power supply

VSS

3

Ground

GND

OUT

4

Output

Clock signal output

PDWN

5

Input

Power-down control *

1

SEL

6

Input

Frequency select *

1

IN

7

Input

Clock signal input *

1

DIV2

8

Input

Frequency select *

1

Note:

1. LVCMOS level input. Pull-down by internal resistor (100 k

Ω).

Power-down Function Table

PDWN

IC Operating

OUTPUT

Remark

L

Power-down

Low level

Default *

1

H

Active

Clock signal output

Note:

1. All Circuits are set stand-by condition.

Clock Frequency Table

SEL

DIV2

Output Frequency

(IN:OUT Ratio)

Remark

L

27.0 MHz (1:1)

Default

H

L

33.75 MHz (1:1.25)

L

H

13.5 MHz (1:0.5)

H

16.875 MHz (1:0.625)

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