R1LV0216BSB

R10DS0051EJ0100 Rev.1.00

Page 8 of 14

2011.03.30

Write Cycle

R1LV0216BSB-5S*

R1LV0216BSB-7S*

Parameter

Symbol

Min.

Max.

Min.

Max.

Unit

Note

Write cycle time

55

-

70

-

ns

Address valid to end of write

50

-

55

-

ns

Chip select to end of write

50

-

55

-

ns

5

Write pulse width

45

-

50

-

ns

4

LB#, UB# valid to end of write

50

-

55

-

ns

Address setup time

0

-

0

-

ns

6

Write recovery time

0

-

0

-

ns

7

Data to write time overlap

25

-

30

-

ns

Data hold from write time

0

-

0

-

ns

Output enable from end of write

5

-

5

-

ns

2

Output disable to output in high-Z

0

20

0

25

ns

1,2

Write to output in high-Z

0

20

0

25

ns

1,2

Note

referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

device to device.

4. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB#.

A write begins at the latest transition among CS# going low, WE# going low and LB# going low or UB# going

low.

A write ends at the earliest transition among CS# going high, WE# going high and LB# going high or UB#

going high.

8. Don’t apply inverted phase signal externally when DQ pin is output mode.