μPD44164184B

R10DS0015EJ0200 Rev.2.00

Page 8 of 32

October 6, 2011

Burst Sequence

Linear Burst Sequence Table

A1, A0

A1, A0

A1, A0

A1, A0

External Address

0, 0

0, 1

1, 0

1, 1

1st Internal Burst Address

0, 1

1, 0

1, 1

0, 0

2nd Internal Burst Address

1, 0

1, 1

0, 0

0, 1

3rd Internal Burst Address

1, 1

0, 0

0, 1

1, 0

Truth Table

Operation

LD# R, W#

CLK

DQ

WRITE cycle

L

L

L

→ H

Data in

Load address, input write data on

Input data

D(A1)

D(A2)

D(A3)

D(A4)

consecutive K and K# rising edge

Input clock

K(t+1)

↑ K#(t+1) ↑ K(t+2) ↑↑ K#(t+2) ↑

READ cycle

L

H

L

→ H

Data out

Load address, read data on

Output data

Q(A1)

Q(A2)

Q(A3)

Q(A4)

consecutive C and C# rising edge

Output clock C#(t+1)

↑ C(t+2) ↑ C#(t+2) ↑ C(t+3) ↑

NOP (No operation)

H

×

L

→ H

High-Z

Clock stop

×

×

Stopped Previous state

Remarks 1. H : HIGH, L : LOW,

× : don’t care, ↑ : rising edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges

except if C and C# are HIGH then Data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup/hold times around the rising edge (LOW to HIGH) of

K. All control inputs are registered during the rising edge of K.

4. This device contains circuitry that ensure the outputs to be in high impedance during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. A1 refers to the address input during a WRITE or READ cycle. A2, A3 and A4 refers to the next internal

burst address in accordance with the linear burst sequence.

7. It is recommended that K = K# = C = C# when clock is stopped. This is not essential but permits most

rapid restart by overcoming transmission line charging symmetrically.