4

Block Functions

(1) Address management circuit

The address management circuit converts addresses transferred from the system through A0 to A16 into addresses

compatible with the memory map of the built-in RAM. This function can be used to address up to 480 x 320 dots with

four of these LSIs, thus making it possible to configure a liquid crystal display system without difficulty. Moreover,

addresses 1FFF0H to 1FFFFH are allocated to the gray scale pallet register, making it possible to choose any 4 gray

scales from the 25-level pallet.

(2) Arbiter

The arbiter adjusts the contention between the RAM access from the system and the RAM read on the liquid-crystal

drive side.

(3) RAM

Static RAM (single port) of 240 by 160 by 2 bits

(4) Data bus control

This circuit controls the data transfer directions through the read/write from the system. It also performs an 8/16-bit

switch via the BMODE pin.

(5) Gray scale generation circuit

This circuit realizes the 25 levels by frame thinning out and pulse width modulation.

(6) Internal timing generation

Internal timing to each block is generated from /FRM and STB signals.

(7) CR oscillator

The CR oscillator generates the clock which will become a criterion of the frame frequency in master mode. 1/2592

of this oscillation becomes the frame frequency. For example, if the frame frequency is 70 Hz, the required oscillation

frequency is 181.44 kHz. As the CR oscillator has a built-in capacitor, adjust the required oscillation frequency with

an external resistor.

In slave mode, the oscillation is stopped.

(8) Liquid crystal timing generation

In master mode, /FRM (frame signal), STB (column drive signal strobe), and PULSE (25-gray-sc ale pallet pulse

modulation clock) are generated.

(9) Gray scale control

This circuit realizes a four-gray scale display.

(10) Data latch (1)

Reads and latches 240-pixel data from the RAM.

(11) Data latch (2)

Latches 240-pixel data synchronously with the STB signal.