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DAC39J82 Datasheet(PDF) 1 Page - Texas Instruments |
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DAC39J82 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 144 page  DAC39J82 16-bit DAC 16-bit DAC xN xN RF Product Folder Sample & Buy Technical Documents Tools & Software Support & Community DAC39J82 SLASE47 – JANUARY 2015 DAC39J82 Dual-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface 1 Features 3 Description The DAC39J82 is a very low power, 16-bit, dual- 1 • Resolution: 16-Bit channel, 2.8 GSPS digital to analog converter (DAC) • Maximum Sample Rate: 2.8GSPS with JESD204B interface. The maximum input data • Maximum Input Data Rate: 1.4GSPS rate is 1.4 GSPS. • JESD204B Interface Digital data is input to the device through 1, 2, 4 or 8 – 8 JESD204B Serial Input Lanes configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and – 12.5 Gbps Maximum Bit Rate per Lane programmable equalization. The interface allows – Subclass 1 Multi-DAC synchronization JESD204B Subclass 1 SYSREF based deterministic • On-Chip Very Low Jitter PLL latency and full synchronization of multiple devices. • Selectable 1x -16x Interpolation The device includes features that simplify the design • Independent Complex Mixers with 48-bit NCO/ or of complex transmit architectures. Fully bypassable ±n×Fs/8 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and • Wideband Digital Quadrature Modulator reconstruction filters. An on-chip 48-bit Numerically Correction Controlled Oscillator (NCO) and independent • Sinx/x Correction Filters complex mixers allow flexible and accurate carrier • Fractional Sample Group Delay Correction placement. • Flexible Routing to Four Analog Outputs via A high-performance low jitter PLL simplifies clocking Output Multiplexer of the device without significant impact on the dynamic range. The digital Quadrature Modulator • 3/4-Wire Serial Control Bus (SPI) Correction (QMC) and Group Delay Correction (QDC) • Integrated Temperature Sensor enable complete IQ compensation for gain, offset, • JTAG Boundary Scan phase, and group delay between channels in direct • Pin-compatible with Quad-channel DAC39J84 up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to • Power Dissipation: 1.1W at 2.8GSPS provide PA protection in cases when the abnormal • Package: 10x10mm, 144-Ball Flip-Chip BGA power behavior of the input data is detected. DAC39J82 provides four analog outputs, and the 2 Applications data from the internal two digital paths can be routed • Cellular Base Stations to any two out of these four DAC outputs via the • Diversity Transmit output multiplexer. • Wideband Communications Device Information(1) • Direct Digital Synthesis (DDS) Instruments PART NUMBER PACKAGE BODY SIZE (NOM) • Millimeter/Microwave Backhaul DAC39J82 FCBGA (144) 10.00 mm x 10.00 mm • Automated Test Equipment (1) For all available packages, see the orderable addendum at • Cable Infrastructure the end of the datasheet. • Radar 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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