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UPD16312 Datasheet(PDF) 4 Page - NEC

Part No. UPD16312
Description  1/4- to 1/11-DUTY FIPTM VFD CONTROLLER/DRIVER
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Maker  NEC [NEC]
Homepage  http://www.nec.com/
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 4 page
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4
PD16312
Pin Function
Symbol
Pin Name
Pin No
Description
DIN
Data input
6
Input serial data at rising edge of shift clock, starting from the low
order bit.
DOUT
Data output
5
Output serial data at the falling edge of the shift clock, starting
from low order bit. This is N-ch open-drain output pin.
STB
Strobe
9
Initializes serial interface at the rising or falling edge of the
PD16312. It then waits for reception of a command. Data input
after STB has fallen is processed as a command. While
command data is processed, current processing is stopped, and
the serial interface is initialized. While STB is high, CLK is
ignored.
CLK
Clock input
8
Reads serial data at the rising edge, and outputs data at the
falling edge.
OSC
Oscillator pin
44
Connect resistor to this pin to determine the oscillation frequency
to this pin.
Seg1/KS1 to
Seg6/KS6
High-voltage output
15 to 20
Segment output pins (Dual function as key source)
Seg7 to Seg11
High-voltage output
(segment)
21 to 25
Segment output pins
Grid1 to Grid6
High-voltage output (grid)
37 to 32
Grid output pins
Seg12/Grid11 to
Seg16/Grid7
High-voltage output
(segment/grid)
26, 28 to 31
These pins are selectable for segment or grid driving.
LED1 to LED4
LED output
42 to 39
CMOS output. +20 mA max.
KEY1 to KEY4
Key data input
10 to 13
Data input to these pins is latched at the end of the display cycle.
SW1 to SW4
Switch input
1 to 4
These pins constitute a 4-bit general-purpose input port.
VDD
Logic power
14, 38
5 V
 10 %
VSS
Logic ground
7, 43
Connect this pin to system GND.
VEE
Pull-down level
27
VDD
 35 V max.




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