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UPC8130TA-E3 Datasheet(PDF) 3 Page - NEC |
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UPC8130TA-E3 Datasheet(HTML) 3 Page - NEC |
3 / 40 page 3 µµµµPC8130TA, µµµµPC8131TA 2 1 4 5 3 Bias circuit GND Control circuit Control circuit 2 6 5 PIN EXPLANATION Pin No. Pin Name Applied Voltage V Pin Voltage V Note Function and Applications Internal Equivalent Circuit 1 IN – 1.4 RF input pin. This pin should be coupled with capacitor (eg 1000 pF) for DC cut. Input return loss can be improved with external impedance matching circuit. 2 3 GND 0 − Ground pin. This pin should be connected to system ground with minimum inductance. Ground patt- ern on the board should be formed as wide as possible. Ground pins must be connected together with wide ground pattern to decrease impedance difference. 4 OUT voltage as same as VCC through external inductor − RF output pin. This pin is designed as open collector of high impedance. This pin must be externally equipped with matching circuits. 5VCC 2.7 to 3.3 – Supply voltage pin. This pin must be equipped with bypass capacitor (eg 1000 pF) to minimize its RF impedance. 6VAGC 0 to 3.3 − Gain control pin. The relation between product number and control performance is shown below; Note Pin voltage is measured at VCC = 3.0 V. Part No. VAGC up vs. Gain µPC8130TA up µPC8131TA down |
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