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SSM2404 Datasheet(PDF) 7 Page - Analog Devices |
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SSM2404 Datasheet(HTML) 7 Page - Analog Devices |
7 / 8 page SSM2404 REV. B –7– DETAILED SWITCH OPERATION A simplified circuit schematic with the functional sections is shown in Figure 21. The TTL interface has an internally regulated 5 V to ensure TTL logic levels regardless of the supply voltage. The logic threshold is with respect to the DGND pin, which can be offset. For example, if DGND is connected to the negative supply, then the SSM2404 will operate with negative rail logic. The interface shifts the control logic down to the negative supply and inverts it to drive N1. SW CONTROL DGND TTL INTERFACE BREAK-BEFORE-MAKE RAMP GENERATOR SW1 A SW1 B BIAS N1 P1 C1 15pF P2 N3 V– V+ N4 P4 –1 –1 P3 N2 100nA 100nA C2 15pF Figure 21. Simplified Schematic N1 in combination with C1 and the 100 nA current source provides the break-before-make operation of the switch. When the switch is on, N1 is off and C1 is charged up to the positive rail. However, when the SW CONTROL is turned off, then the gate of N1 is pulled high. This turns N1 on, providing a low impedance path to quickly discharge C1 to the negative rail, which quickly “breaks” the switch. On the other hand, when the SW CONTROL goes high again, the gate of N1 is pulled low, turning it off. This leaves C1 to be slowly charged up to the positive rail by the 100 nA current source. The difference in the discharge and charging times ensures break-before-make operation, even from device to device. The voltage on C1 is inverted by P1 to drive the ramp generator differential pair, consisting of P2, P3 and N2, N3. This dif- ferential pair steers the 100 nA of tail current to either charge or discharge C2. As discussed above, when the switch is on, C1 is charged up to the positive rail. P1 inverts this, putting a low voltage equivalent to the negative supply on the gate of P2. The BIAS voltage is approximately equal to the midpoint of the two supply voltages. Thus, when P2 is pulled down, it is turned on and P3 is off. All of the 100 nA flows through N2 and is mir- rored by N3. Thus, the 100 nA discharges C2 through N3. When C2 is pulled low, the inverter turns N4 on by pulling its gate high, and the second inverter turns P4 on. To turn the switch off the gate of P2 is pulled above the BIAS so that all 100 nA charges C2 through P3. This is then inverted to turn off N4 and P4. The internal ramp has rise and fall times on the order of a few milliseconds which is sped up by the inverters. As the gate voltages of N4 and P4 are changing, the ON resistance of each switch is ramping from its OFF state to 28 Ω and vice versa. The actual rise and fall times are shown in Figures 18 and 19 for a 5 k Ω load. These times are significantly slower than typical switches, minimizing the SSM2404’s charge injection and giving it “clickless” performance. DOUBLE-POLE DOUBLE-THROW SWITCH The SSM2404 is ideal as a one-chip solution for a stereo switch. The schematic in Figure 22 shows the typical configura- tion. This circuit will select one of two stereo sources, channel A or B. The switch controls for the left and right input of each channel are tied together so that both will be turned on or off simultaneously. An inverter is inserted between the channel A and B controls so that only one logic signal is needed. The out- puts can be configured many different ways, such as an invert- ing or noninverting amplifier stage, and the 10 k Ω load resistors are added to improve the OFF-isolation. The performance of this stereo switch is equivalent to each individual switch, yield- ing a high quality audio switch that is virtually transparent to the signal. LINA LINB SW2 SW1 SW2 CONTROL SW3 CONTROL DGND SW1 CONTROL SW4 CONTROL RINA RINB SW3 SW4 AGND 10k Ω 10k Ω SSM2404 V– SWA/SWB V+ 17 10 8 13 LOUT 2 ROUT 9 12 19 13 18 14 20 11 16 5 4 15 6 SWA/SWB CHANNEL SELECTED 0 1 B A Figure 22. Double-Pole, Double-Throw Stereo Switch VIRTUAL GROUND SWITCHING The SSM2404 was built on a CMOS process with a 24 V operating limit for the total supply voltage across the part. This leads to a corresponding limit on the analog voltage range. How- ever, to achieve larger signal swings, the SSM2404 should be configured in the virtual ground mode. As shown in Figure 23, the output of the SSM2404 is connected to the inverting input of an amplifier. Since the noninverting input is grounded, the SSM2404 will also be biased at ground, and large voltage swings on the circuit’s input will not significantly change the voltage on the switch. The only limitation is that the current through the switch needs to be less than ±10 mA, and the voltage range is limited only by the op amp and its supply voltages. |
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