RL78/L13

1.

OUTLINE

Page 11 of 11

R01DS0168EJ0002

Rev.0.02

2012.10.31

Under development

Preliminary document

Specifications in this document are tentative and subject to change.

(2/2)

64-pin

80-pin

Item

R5F10WLx

R5F10WMx

2

Clock output/buzzer output

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz

• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz

8/10-bit resolution A/D converter

9 channels

12 channels

Comparator

2 channels

Serial interface

[64-pin]

• UART: 1 channel

[80-pin]

• UART: 2 channels

I

1 channel

LCD controller/driver

Internal voltage boosting method, capacitor split method, and external resistance division method

are switchable.

Segment signal output

36 (32)

Note 1

51 (47)

Note 1

Common signal output

4 (8)

Note 1

Multiplier and

divider/multiply-accumulator

• 16 bits × 16 bits = 32 bits (Unsigned or signed)

• 32 bits ÷ 32 bits = 32 bits (Unsigned)

• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

DMA controller

4 channels

Internal

32

35

Vectored

interrupt sources

External

11

11

Key interrupt

8

8

Reset

• Reset by RESET pin

• Internal reset by watchdog timer

• Internal reset by power-on-reset

• Internal reset by voltage detector

• Internal reset by RAM parity error

• Internal reset by illegal-memory access

Power-on-reset circuit

• Power-on-reset:

1.51

±0.03 V

• Power-down-reset: 1.50 ±0.03 V

Voltage detector

• Rising edge : 1.67 V to 4.06 V (14 stages)

• Falling edge : 1.63 V to 3.98 V (14 stages)

On-chip debug function

Provided

Power supply voltage

Operating ambient temperature

−40 to +85 °C

−40°C to + 105°C

Notes 1.

The values in parentheses are the number of signal outputs when 8 com is used.

2.

The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or

on-chip debug emulator.

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