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RL78L13 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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RL78L13 Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 14 page RL78/L13 1. OUTLINE Page 11 of 11 R01DS0168EJ0002 Rev.0.02 2012.10.31 Under development Preliminary document Specifications in this document are tentative and subject to change. (2/2) 64-pin 80-pin Item R5F10WLx R5F10WMx 2 Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.768 kHz operation) 8/10-bit resolution A/D converter 9 channels 12 channels Comparator 2 channels Serial interface [64-pin] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • UART: 1 channel [80-pin] • CSI: 1 channel/UART (UART supporting LIN-bus): 1 channel/simplified I2C: 1 channel • CSI: 1 channel/UART: 1 channel/simplified I2C: 1 channel • UART: 2 channels I 2C bus 1 channel LCD controller/driver Internal voltage boosting method, capacitor split method, and external resistance division method are switchable. Segment signal output 36 (32) Note 1 51 (47) Note 1 Common signal output 4 (8) Note 1 Multiplier and divider/multiply-accumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) DMA controller 4 channels Internal 32 35 Vectored interrupt sources External 11 11 Key interrupt 8 8 Reset • Reset by RESET pin • Internal reset by watchdog timer • Internal reset by power-on-reset • Internal reset by voltage detector • Internal reset by illegal instruction execution Note • Internal reset by RAM parity error • Internal reset by illegal-memory access Power-on-reset circuit • Power-on-reset: 1.51 ±0.03 V • Power-down-reset: 1.50 ±0.03 V Voltage detector • Rising edge : 1.67 V to 4.06 V (14 stages) • Falling edge : 1.63 V to 3.98 V (14 stages) On-chip debug function Provided Power supply voltage VDD = 1.6 to 5.5 V Operating ambient temperature Consumer application: TA = −40 to +85 °C Industrial application: TA = −40°C to + 105°C Notes 1. The values in parentheses are the number of signal outputs when 8 com is used. 2. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. <R> <R> |
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