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R8CM13B Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R8CM13B Datasheet(HTML) 11 Page - Renesas Technology Corp |
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11 / 51 page  R8C/M13B Group 2. Central Processing Unit (CPU) R01DS0005EJ0200 Rev.2.00 Page 11 of 48 Mar 19, 2012 2.1 Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 through R3. R0 can be split into high-order (R0H) and low-order (R0L) registers to be used separately as 8-bit data registers. The same applies to R1H and R1L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). In the same way as with R0 and R2, R3 and R1 can be used as a 32-bit data register (R3R1). 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 functions in the same manner as A0. A1 can be combined with A0 and used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table. 2.5 Program Counter (PC) PC is a 20-bit register that indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of the FLG register is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register used for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register that indicates the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated in the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. It must only be set to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0. Otherwise it is set to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value. Otherwise it is set to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow. Otherwise it is set to 0. |
Similar Part No. - R8CM13B_15 |
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Similar Description - R8CM13B_15 |
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