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ADUM1250 Datasheet(PDF) 10 Page - Analog Devices |
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ADUM1250 Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page ADuM1250/ADuM1251 Data Sheet Rev. G | Page 10 of 16 APPLICATIONS INFORMATION FUNCTIONAL DESCRIPTION The ADuM1250/ADuM1251 interface on each side to a bidirectional I2C signal. Internally, the I2C interface is split into two unidirectional channels communicating in opposing directions via a dedicated iCoupler isolation channel for each. One channel (the bottom channel of each channel pair shown in Figure 6) senses the voltage state of the Side 1 I2C pin and transmits its state to its respective Side 2 I2C pin. Both the Side 1 and the Side 2 I2C pins are designed to interface to an I2C bus operating in the 3.0 V to 5.5 V range. A logic low on either pin causes the opposite pin to be pulled low enough to comply with the logic low threshold requirements of other I2C devices on the bus. Avoidance of I2C bus contention is ensured by an input low threshold at SDA1 or SCL1 guaranteed to be at least 50 mV less than the output low signal at the same pin. This prevents an output logic low at Side 1 being transmitted back to Side 2 and pulling down the I2C bus. Because the Side 2 logic levels/thresholds are standard I2C values, multiple ADuM1250/ADuM1251 devices connected to a bus by their Side 2 pins can communicate with each other and with other I2C-compatible devices. A distinction is made between I2C compat- ibility and I2C compliance. I2C compatibility refers to situations in which the logic levels of a component do not necessarily meet the requirements of the I2C specification but still allow the component to communicate with an I2C-compliant device. I2C compliance refers to situations in which the logic levels of a component meet the requirements of the I2C specification. However, because the Side 1 pin has a modified output level/ input threshold, this side of the ADuM1250/ADuM1251 can communicate only with devices that conform to the I2C stan- dard. In other words, Side 2 of the ADuM1250/ADuM1251 is I2C-compliant, whereas Side 1 is only I2C-compatible. The output logic low levels are independent of the VDD1 and VDD2 voltages. The input logic low threshold at Side 1 is also independent of VDD1. However, the input logic low threshold at Side 2 is designed to be at 0.3 VDD2, consistent with I2C require- ments. The Side 1 and Side 2 pins have open-collector outputs whose high levels are set via pull-up resistors to their respective supply voltages. ENCODE DECODE DECODE ENCODE ENCODE DECODE DECODE ENCODE VDD1 SDA1 SCL1 VDD2 SDA2 SCL2 CL GND2 1 2 3 8 7 6 5 GND1 4 CL R2 R2 Figure 6. ADuM1250 Block Diagram STARTUP Both the VDD1 and VDD2 supplies have an undervoltage lockout feature to prevent the signal channels from operating unless certain criteria are met. This feature prevents input logic low signals from pulling down the I2C bus inadvertently during power-up/power-down. For the signal channels to be enabled, the following two criteria must be met: • Both supplies must be at least 2.5 V. • At least 40 μs must elapse after both supplies exceed the internal startup threshold of 2.0 V. Until both criteria are met for both supplies, the ADuM1250/ ADuM1251 outputs are pulled high, ensuring a startup that avoids any disturbances on the bus. Figure 7 and Figure 8 illustrate the supply conditions for fast and slow input supply slew rates. MINIMUM RECOMMENDED OPERATING SUPPLY, 3.0V MINIMUM VALID SUPPLY, 2.5V INTERNAL START-UP THRESHOLD, 2.0V 40µs SUPPLY VALID Figure 7. Start-Up Condition, Supply Slew Rate > 12.5 V/ms 40µs SUPPLY VALID MINIMUM RECOMMENDED OPERATING SUPPLY, 3.0V MINIMUM VALID SUPPLY, 2.5V INTERNAL START-UP THRESHOLD, 2.0V Figure 8. Start-Up Condition, Supply Slew Rate < 12.5 V/ms |
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Similar Description - ADUM1250_15 |
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