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ADSP-BF542 Datasheet(PDF) 10 Page - Analog Devices

Part # ADSP-BF542
Description  Blackfin Embedded Processor
Download  102 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-BF542 Datasheet(HTML) 10 Page - Analog Devices

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Rev. E
|
Page 10 of 102
|
March 2014
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Host DMA Port Interface
The host DMA port (HOSTDP) facilitates a host device external
to the ADSP-BF54x Blackfin processors to be a DMA master
and transfer data back and forth. The host device always masters
the transactions, and the processor is always a DMA slave
device.
The HOSTDP is enabled through the peripheral access bus.
Once the port has been enabled, the transactions are controlled
by the external host. The external host programs standard DMA
configuration words in order to send/receive data to any valid
internal or external memory location. The host DMA port con-
troller includes the following features:
• Allows an external master to configure DMA read/write
data transfers and read port status
• Uses a flexible asynchronous memory protocol for its
external interface
• Allows an 8- or 16-bit external data interface to the host
device
• Supports half-duplex operation
• Supports little/big endian data transfers
• Acknowledge mode allows flow control on host
transactions
• Interrupt mode guarantees a burst of FIFO depth host
transactions
REAL-TIME CLOCK
The ADSP-BF54x Blackfin processors’ real-time clock (RTC)
provides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a 32.768 kHz
crystal external to the ADSP-BF54x Blackfin processors. The
RTC peripheral has dedicated power supply pins so that it can
remain powered up and clocked even when the rest of the pro-
cessor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per sec-
ond, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and a 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms. The first alarm is
for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed value
with one-second resolution. When the stopwatch is enabled and
the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the
ADSP-BF54x processor from sleep mode upon generation of
any RTC wakeup event. Additionally, an RTC wakeup event can
wake up the ADSP-BF54x processors from deep sleep mode,
and it can wake up the on-chip internal voltage regulator from
the hibernate state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
WATCHDOG TIMER
The ADSP-BF54x processors include a 32-bit timer that can be
used to implement a software watchdog function. A software
watchdog can improve system reliability by forcing the proces-
sor to a known state through generation of a hardware reset,
non-maskable interrupt (NMI), or general-purpose interrupt if
the timer expires before being reset by software. The program-
mer initializes the count value of the timer, enables the
appropriate interrupt, and then enables the timer. Thereafter,
the software must reload the counter before it counts to zero
from the programmed value. This protects the system from
remaining in an unknown state where software, which would
normally reset the timer, has stopped running due to an external
noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF54x processors’ peripher-
als. After a reset, software can determine if the watchdog was the
source of the hardware reset by interrogating a status bit in the
watchdog timer control register.
The timer is clocked by the system clock (SCLK) at a maximum
frequency of fSCLK.
TIMERS
There are up to two timer units in the ADSP-BF54x Blackfin
processors. One unit provides eight general-purpose program-
mable timers, and the other unit provides three. Each timer has
an external pin that can be configured either as a pulse width
modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and peri-
ods of external events. These timers can be synchronized to an
external clock input on the TMRx pins, an external clock
TMRCLK input pin, or to the internal SCLK.
Figure 4. External Components for RTC
RTXO
C1
C2
X1
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)
C1 = 22 pF
C2 = 22 pF
R1 = 10 M
Ω
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.
RTXI
R1


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