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ISL83490 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL83490 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 17 page 7 Driver Disable from Output Low (Except ISL83488) tLZ RL = 110Ω, CL = 50pF, SW = VCC (Figure 3) 25 - 70 80 ns Full - - 110 ns Driver Enable from Shutdown to Output High (Except ISL83488) tZH(SHDN) RL = 110Ω, CL = 50pF, SW = GND (Notes 7, 8) Full - 450 2000 ns Driver Enable from Shutdown to Output Low (Except ISL83488) tZL(SHDN) RL = 110Ω, CL = 50pF, SW = VCC (Figure 3), (Notes 7, 8) Full - 126 2000 ns RECEIVER SWITCHING CHARACTERISTICS (All Versions) Receiver Input to Output Delay tPLH, tPHL (Figure 4) Full 25 45 90 ns Receiver Skew | tPLH - tPHL |tSKD (Figure 4) 25 - 2 10 ns Full - 2 12 ns Receiver Enable to Output High (Except ISL83488 and ISL83490) tZH RL = 1kΩ, CL = 15pF, SW = GND (Figure 5), (Note 6) Full - 11 50 ns Receiver Enable to Output Low (Except ISL83488 and ISL83490) tZL RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5), (Note 6) Full - 11 50 ns Receiver Disable from Output High (Except ISL83488 and ISL83490) tHZ RL = 1kΩ, CL = 15pF, SW = GND (Figure 5) Full - 7 45 ns Receiver Disable from Output Low (Except ISL83488 and ISL83490) tLZ RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5) Full - 7 45 ns Time to Shutdown (Except ISL83488 and ISL83490) tSHDN (Note 7) Full 80 190 300 ns Receiver Enable from Shutdown to Output High (Except ISL83488 and ISL83490) tZH(SHDN) RL = 1kΩ, CL = 15pF, SW = GND (Figure 5), (Notes 7, 9) Full - 240 600 ns Receiver Enable from Shutdown to Output Low (Except ISL83488 and ISL83490) tZL(SHDN) RL = 1kΩ, CL = 15pF, SW = VCC (Figure 5), (Notes 7, 9) Full - 240 600 ns NOTES: 2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 3. Supply current specification is valid for loaded drivers when DE = 0V. 4. Applies to peak current. See “Typical Performance Curves” for more information. 5. When testing the ISL83483, ISL83485, ISL83491, keep RE = 0 to prevent the device from entering SHDN. 6. When testing the ISL83483, ISL83485, ISL83491, the RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN. 7. The ISL83483, ISL83485, ISL83491 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80ns, the parts are guaranteed not to enter shutdown. If the inputs are in this state for at least 300ns, the parts are guaranteed to have entered shutdown. See “Low-Power Shutdown Mode” section. 8. Keep RE = VCC, and set the DE signal low time >300ns to ensure that the device enters SHDN. 9. Set the RE signal high time >300ns to ensure that the device enters SHDN. Electrical Specifications Test Conditions: VCC = 3V to 3.6V; Unless Otherwise Specified. Typicals are at VCC = 3.3V, TA = 25oC, Note 2 (Continued) PARAMETER SYMBOL TEST CONDITIONS TEMP (oC) MIN TYP MAX UNITS ISL83483, ISL83485, ISL83488, ISL83490, ISL83491 |
Similar Part No. - ISL83490 |
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Similar Description - ISL83490 |
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