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ISL6565ACRZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6565ACRZ Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 28 page  11 Figures 19 and 20 in the section entitled Input Capacitor Selection can be used to determine the input-capacitor RMS current based on load current, duty cycle, and the number of channels. They are provided as aids in determining the optimal input capacitor solution. PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6565A, ISL6565B is three. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is the internally generated clock signal that triggers the falling edge of PWM1. The cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. Each cycle begins when the clock signal commands PWM1 to go low. The PWM1 transition signals the channel-1 MOSFET driver to turn off the channel-1 upper MOSFET and turn on the channel-1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1/3 of a cycle after the PWM1 pulse. The PWM3 pulse terminates 1/3 of a cycle after PWM2. If PWM3 is connected to VCC, two channel operation is selected and the PWM2 pulse terminates 1/2 of a cycle after the PWM1 pulse terminates. Once a PWM pulse transitions low, it is held low for a minimum of 1/3 cycle. This forced off time is required to ensure an accurate current sample. Current sensing is described in the next section. After the forced off time expires, the PWM output is enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the current correction signal relative to the sawtooth ramp as illustrated in Figure 6. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output transitions high. The MOSFET driver detects the change in state of the PWM signal and turns off the synchronous MOSFET and turns on the upper MOSFET. The PWM signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the PWM signal low. Current Sampling During the forced off-time, following a PWM transition low, the current-sense amplifier uses the ISEN inputs to reproduce a signal proportional to the inductor current, IL. No matter which current-sense method is employed, the sense current (ISEN) is simply a scaled version of the inductor current. The sample window opens exactly 1/6 of the switching period, tSW, after the PWM transitions low. The sample window then stays open for a fixed amount of time, tSAMPLE, and is equal to 1/6 of the switching period, tSW as illustrated in Figure 3. The sampled current, at the end of the tSAMPLE, is proportional to the inductor current and is held until the next switching period sample. The sampled current is used for current balance, load-line regulation, and overcurrent protection. Current Sensing The ISL6565A supports MOSFET rDS(ON) current sensing, while the ISL6565B supports inductor DCR current sensing. The internal circuitry, shown in Figures 4 and 5, represent channel n of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending on the status of the PWM3 pin, as described in the PWM Operation section. MOSFET rDS(ON) SENSING (ISL6565A ONLY) The ISL6565A senses the channel load current by sampling the voltage across the lower MOSFET rDS(ON), as shown in Figure 4. A ground-referenced operational amplifier, internal to the ISL6565A, is connected to the PHASE node through a resistor, RISEN. The voltage across RISEN is equivalent to the voltage drop across the rDS(ON) of the lower MOSFET while it is conducting. The resulting current into the ISEN pin is proportional to the channel current, IL. The ISEN current is sampled and held as described in the Current Sampling section. From Figure 4, the following equation for In is derived where IL is the channel current. tSAMPLE tSW 6 ---------- 1 6fSW ⋅ ------------------ == (EQ. 3) FIGURE 3. SAMPLE AND HOLD TIMING TIME PWM IL ISEN NEW SAMPLE CURRENT tSAMPLE SWITCHING PERIOD OLD SAMPLE CURRENT In IL rDS ON () RISEN ---------------------- = (EQ. 4) ISL6565A, ISL6565B |
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