8

FN9082.4

a suitable supply, 5V to 10V, no higher than the voltage

applied at the VCC pin. The higher the voltage applied at the

PVCC pin, the better the channel enhancement of the on-

board power MOSFETs, but also the higher the power

dissipated inside the driver.

The down-conversion voltage applied at VIN cannot exceed

the bias voltage applied at VCC, but can be as low as

practically possible.

Operation

The ISL6571 combines two MOSFET transistors in a

synchronous buck power train configuration, along with a half-

bridge MOSFET driver designed to control these two

MOSFETs. When reviewing the operational details, refer to

Figure 5 test setup.

With all requirements for operation met, a logic high signal

on the PWM pin causes the UFET to turn on, while a logic

low signal applied to the PWM pin causes LFET to turn on. If

the PWM input is driven within the shutdown window and

remains there for the minimum holdoff time specified (See

‘Electrical Specifications’), both MOSFETs are turned off.

At the transition between the on intervals of the two

MOSFETs, the internal driver acts in a ‘break-before-make’

fashion. Thus, the driver monitors the on device and turns on

the (previously) off device, following a short time delay after

the on MOSFET has turned off. This behavior is necessary

to insure the absence of cross-conduction (shoot-through)

amongst the two MOSFETs.

Application and Component Selection

Guidelines

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turn-off

transition of the upper MOSFET. Prior to turn-off, the upper

MOSFET was carrying the full load current. During the turn-

off, current stops flowing in the upper MOSFET and is picked

up by the lower MOSFET or Schottky diode. Any inductance

in the switched current path generates a large voltage spike

during the switching interval. Careful component selection,

tight layout of the critical components, and short, wide circuit

traces minimize the magnitude of voltage spikes.

The ISL6571 is the first step in such an efficient design. By

bringing the driver and switching transistors in close

proximity, most of the interconnect/layout parasitic

inductances are greatly reduced. However, these benefits

are nulled if the associated decoupling elements and other

circuit components are not carefully positioned and laid out

to help the ISL6571 realize its full potential. Figure 12 shows

one possible layout pattern, detailing preferred positioning of

components, land size/pattern, and via count. Figure 12 is

one of many possible layouts yielding good results; use it for

general illustration and guidance.

Locate the decoupling capacitors, especially the high-

frequency ceramic capacitors, close to the ISL6571. To fully

exploit ceramic capacitors’ low equivalent series inductance

(ESL), insure their ground connection is made as close to

their grounded terminal as physically feasible. Figure 12

details via-in-pad (VIP) practices, where the via is placed on

the component’s landing pad, thus yielding the shortest-

path, lowest ESL connection to the desired plane/island.

Via-in-pad design is very important to the layout of the

ISL6571, since it is an integral part of the thermal design

consideration. VIP not only provides the lowest ESL circuit

connections, but it is essential to the propagation of heat

from the internal dies to the ambient. The vias placed directly

underneath the bottom pads of the package provide a low

thermal impedance path for the heat generated inside the IC

to diffuse through the internal planes, as well as through

islands on the back side of the board. Layout with landing

pads for the bottom pads of the package devoid of vias is

possible (rather, with vias placed outside of the package

outline), but the thermal performance of such a layout would

be significantly reduced. Use the smallest diameter vias

available and avoid the use of thermal relief on the contacts

with internal planes; if thermal relief is mandatory on all vias,

design the thermal relief so that it voids the smallest possible

copper area around the vias (thus preserving thermal

conductivity and reducing electrical contact resistance).

A multi-layer printed circuit board is recommended. Dedicate

one solid layer for a ground plane and make all critical

component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break this

plane into smaller islands of common voltage levels. The

power plane should support the input power and output

power nodes.

FIGURE 11. PHASE RESPONSE TO PWM INPUT

GND

GND

ISL6571