3

FN9066.4

July 8, 2005

9

6

R_LEB

Program the leading edge blanking from 50ns to 300ns.

10

7

CS_COMP

Set a low current sharing loop bandwidth with a capacitor.

11

8

CSS

Program the rise time and the clamping voltage with a capacitor and a resistor, respectively.

12

9

EANI

Non-inverting input of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).

13

10

EAI

Inverting input of Error Amp. It receives the feedback voltage.

14

11

EAO

Output of Error Amp. It is clamped by the voltage at the CSS pin (Vclamp).

15

12

SHARE

This pin is the SHARE BUS connecting with other unit(s) for current share operation.

16

13

LATSD

The IC is latched off with a voltage greater than 3V at this pin and is reset by recycling VDD.

17

14

DCOK

Power Good indication with a ±5% window.

18

15

ON/OFF

This is an Enable pin that controls the states of all drive signals and the soft-start.

19, 20

16, 17

SYNC2, SYNC1

These are the gate control signals for the output synchronous rectifiers.

21, 22

18, 19

LOWER2, LOWER1

Both lower drivers are PWM-controlled on the trailing edge.

23, 24

20, 21

UPPER2, UPPER1

Both upper drivers are driven at a fixed 50% duty cycle.

25

22

PGND

Power Ground. High current return paths for both the upper and the lower drivers.

26, 27

23, 24

VDDP2, VDDP1

Power is delivered to both the upper and the lower drivers through these pins.

28

25

VDD

Power is delivered to all control circuits including SYNC1 & SYNC2 via this pin.

PACKAGE PIN #

PIN SYMBOL

FUNCTION

SOIC

QFN

ISL6551