8

FN9003.3

February 11, 2005

Applications and Converter Start-Up

Each PWM power channel’s current is regulated. This

enables the PWM channels to accurately share the load

current for enhanced reliability. The HIP6601, HIP6602 or

HIP6603 MOSFET driver interfaces with the ISL6554. For

more information, see the HIP6601, HIP6602 or HIP6603

data sheets [1], [2].

The ISL6554 is capable of controlling up to 4 PWM power

channels. Connecting unused PWM outputs to VCC

automatically sets the number of channels. The phase

relationship between the channels is 360 degrees/number of

active PWM channels. For example, for three channel

operation, the PWM outputs are separated by 120 degrees.

Figure 2 shows the PWM output signals for a four channel

system.

Power supply ripple frequency is determined by the channel

channels. For example, if the channel frequency is set to

250kHz and there are three phases, the ripple frequency is

750kHz.

The IC monitors and precisely regulates the CORE voltage

of a microprocessor. After initial start-up, the controller also

provides protection for the load and the power supply. The

following section discusses these features.

Initialization

The ISL6554 usually operates from an ATX power supply.

Many functions are initiated by the rising supply voltage to

the VCC pin of the ISL6554. Oscillator, sawtooth generator,

soft-start and other functions are initialized during this

interval. These circuits are controlled by POR, Power-On

Reset. During this interval, the PWM outputs are driven to a

three state condition that makes these outputs essentially

open. This state results in no gate drive to the output

MOSFETs.

Once the VCC voltage reaches 4.375V (

+125mV), a voltage

level to insure proper internal function, the PWM outputs are

enabled and the soft-start sequence is initiated. If for any

reason, the VCC voltage drops below 3.875V (

+125mV). The

POR circuit shuts the converter down and again three states

the PWM outputs.

Soft-Start

After the POR function is completed with VCC reaching

4.375V, the soft-start sequence is initiated. soft-start, by its

slow rise in CORE voltage from zero, avoids an overcurrent

condition by slowly charging the discharged output

capacitors. This voltage rise is initiated by an internal DAC

that slowly raises the reference voltage to the error amplifier

input. The voltage rise is controlled by the oscillator

frequency and the DAC within the ISL6554, therefore; the

output voltage is effectively regulated as it rises to the final

programmed CORE voltage value.

For the first 32 PWM switching cycles, the DAC output

remains inhibited and the PWM outputs remain three stated.

From the 33rd cycle and for another, approximately 150

cycles, the PWM output remains low, clamping the lower

output MOSFETs to ground (see Figure 3). The time

variability is due to the error amplifier, sawtooth generator

and comparators moving into their active regions. After this

short interval, the PWM outputs are enabled and increment

the PWM pulse width from zero duty cycle to operational

pulse width, thus allowing the output voltage to slowly reach

the CORE voltage. The CORE voltage will reach its

programmed value before the 2048 cycles, but the PGOOD

output will not be initiated until the 2048th PWM switching

cycle.

160

µs, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

described above, the PWM outputs are initiated and the

voltage rises in 10.08ms, for a total delay time DT of 10.24ms.

Figure 3 shows the start-up sequence as initiated by a fast

short rise to the three state level in PWM 1 output during first

32 PWM cycles.

Figure 4 shows the waveforms when the regulator is

operating at 200kHz. Note that the soft-start duration is a

function of the channel frequency as explained previously.

Also note the pulses on the COMP terminal. These pulses

are the current correction signal feeding into the comparator

input (see the Block Diagram).

Figure 5 shows the regulator operating from an ATX supply.

In this figure, note the slight rise in PGOOD as the 5V supply

rises. The PGOOD output stage is made up of NMOS and

PMOS transistors. On the rising VCC, the PMOS device

becomes active slightly before the NMOS transistor pulls

“down”, generating the slight rise in the PGOOD voltage.

PWM 1

PWM 2

PWM 3

PWM 4

FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz

ISL6554