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ISL6529ACR-T Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL6529ACR-T Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 15 page 10 FN9127.1 December 28, 2004 controllable closed loop transfer function of VOUT/VREF. The goal of component selection for the compensation network is to provide a loop gain with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. Compensation Break Frequency Equations Follow this procedure for selecting compensation components by locating the poles and zeros of the compensation network: 1. Set the loop gain (R2/R1) to provide a converter bandwidth of one quarter of the switching frequency. 2. Place the first compensation zero, FZ1, below the output filter double pole (~75% FLC). 3. Position the second compensation zero, FZ2, at the output filter double pole, FLC. 4. Locate the first compensation pole, FP1, at the output filter ESR zero, FESR. 5. Position the second compensation pole at half the converter switching frequency, FSW. 6. Check gain against error amplifier’s open-loop gain. 7. Estimate phase margin; repeat if necessary. Figure 7 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual modulator gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 7. Using the above procedure should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. Linear Regulator Feedback Compensation The regulator may be compensated with a series 6.8k Ω resistor and a 470pF capacitor connected between FB2 and DRIVE2. This will provide compensation for all loads and ranges of output capacitor values and a range of capacitor ESR values from aluminum electrolytic to low-ESR organic polymer capacitors. This will not insure optimum load transient response since the regulator system, like an internally compensated operational amplifier is overcompensated. To optimize transient response, when required, the regulator should be in the actual application circuit with the desired output capacitors and associated PC board parasitics and load. The value of C4 would be reduced and the series resistor, R12 adjusted for optimum rise and fall time, with a minimum of overshoot. Application Guidelines Layout Considerations Layout is very important in high frequency switching converter design. With power devices switching efficiently at 600kHz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. Careful component layout and printed circuit board design minimizes the voltage spikes in the converters. As an example, consider the turn-off transition of the PWM MOSFET. Prior to turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is picked up by the lower MOSFET and parasitic diode. Any parasitic inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide traces minimizes the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using the ISL6529A. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling. F Z1 1 2 π R × 2C1 × ----------------------------------- = F Z2 1 2 π R1 R3 + () C3 × × ------------------------------------------------------- = F P1 1 2 π R 2 C1 C2 × C1 C2 + ---------------------- × × ------------------------------------------------------- = F P2 1 2 π R × 3C3 × ----------------------------------- = (EQ. 10) (EQ. 11) (EQ. 8) (EQ. 9) Zeros: Poles: FIGURE 7. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 100 80 60 40 20 0 -20 -40 -60 FP1 FZ2 10M 1M 100K 10K 1K 100 10 OPEN LOOP ERROR AMP GAIN FZ1 FP2 FLC FESR COMPENSATION FREQUENCY (Hz) GAIN MODULATOR GAIN LOOP GAIN 20 V IN V OSC ------------------ log 20 R2 R1 --------- log ISL6529A |
Similar Part No. - ISL6529ACR-T |
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Similar Description - ISL6529ACR-T |
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