9

FN9015.3

April 18, 2005

quickly discharged. The counter increments to 2. The soft-

start cycle repeats at T3 and trips the overcurrent comparator.

The SS24 pin voltage increases to above 4.0V at T4 and the

counter increments to 3. This sets the fault latch to disable the

converter.

The three linear controllers monitor their respective VSEN

pins for undervoltage. Should excessive currents cause

VSEN3 or VSEN4 to fall below the linear undervoltage

threshold, the respective UV signals set the OC latch or the

interval allows the linear outputs to build above the

undervoltage threshold during normal operation. Cycling the

bias input power off then on resets the counter and the fault

latch.

level for the PWM converter. As shown in Figure 9, the internal

enables the overcurrent comparator (OC). When the voltage

overcurrent comparator trips to set the overcurrent latch. Both

to MOSFET switching. The overcurrent function will trip at a

temperature variations. To avoid overcurrent tripping in the

normal operating load range, determine the ROCSET

resistor value from the equation above with:

where DI is the output inductor ripple current.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

OUT1 Voltage Program

The output voltage of the PWM converter is programmed to

discrete levels between 1.050V and 1.825V. This output

(OUT1) is designed to supply the core voltage of Intel’s

advanced microprocessors. The voltage identification (VID)

pins program an internal voltage reference (DACOUT) with a

TTL-compatible 5-bit digital-to-analog converter (DAC). The

level of DACOUT also sets the PGOOD and OVP thresholds.

Table 1 specifies the DACOUT voltage for the different

combinations of connections on the VID pins. The VID pins

can be left open for a logic 1 input, since they are internally

pulled to the VAUX pin through 5kW resistors. Changing the

VID inputs during operation is not recommended and could

toggle the PGOOD signal and exercise the overvoltage

protection. The output voltage program is Intel VRM8.5

compatible.

FIGURE 8. OVERCURRENT OPERATION

0A

0V

2V

4V

TIME

T1

T2

T3

T0

T4

0V

10V

FAULT

REPORTED

COUNT

= 2

COUNT

= 3

OVERLOAD

APPLIED

COUNT

= 1

×

()

----------------------------------------------------

FIGURE 9. OVERCURRENT DETECTION

UGATE

OCSET

PHASE

OC

+

-

GATE

CONTROL

VCC

200

µA

OVERCURRENT TRIP:

+

+

PWM

DRIVE

VPHASE VIN VDS

–

=

VOCSET VIN VSET

–

=

iD rDS ON

()

×

IOCSET ROCSET

×

>

VDS VSET

>