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ISL6524CBZ-T Datasheet(PDF) 9 Page - Intersil Corporation |
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ISL6524CBZ-T Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 16 page 9 FN9015.3 April 18, 2005 4.0V before discharging. Soft-start capacitor CSS13 is, again, quickly discharged. The counter increments to 2. The soft- start cycle repeats at T3 and trips the overcurrent comparator. The SS24 pin voltage increases to above 4.0V at T4 and the counter increments to 3. This sets the fault latch to disable the converter. The three linear controllers monitor their respective VSEN pins for undervoltage. Should excessive currents cause VSEN3 or VSEN4 to fall below the linear undervoltage threshold, the respective UV signals set the OC latch or the FAULT latch, providing respective CSS capacitors are fully charged. Blanking the UV signals during the CSS charge interval allows the linear outputs to build above the undervoltage threshold during normal operation. Cycling the bias input power off then on resets the counter and the fault latch. An external resistor (ROCSET) programs the overcurrent trip level for the PWM converter. As shown in Figure 9, the internal 200mA current sink (IOCSET) develops a voltage across ROCSET (VSET) that is referenced to VIN. The DRIVE signal enables the overcurrent comparator (OC). When the voltage across the upper MOSFET (VDS(ON)) exceeds VSET, the overcurrent comparator trips to set the overcurrent latch. Both VSET and VDS are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The overcurrent function will trip at a peak inductor current (IPEAK) determined by: The OC trip point varies with MOSFET’s rDS(ON) temperature variations. To avoid overcurrent tripping in the normal operating load range, determine the ROCSET resistor value from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature 2. The minimum IOCSET from the specification table 3. Determine IPEAK for IPEAK > IOUT(MAX) + (DI)/2, where DI is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. OUT1 Voltage Program The output voltage of the PWM converter is programmed to discrete levels between 1.050V and 1.825V. This output (OUT1) is designed to supply the core voltage of Intel’s advanced microprocessors. The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a TTL-compatible 5-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the different combinations of connections on the VID pins. The VID pins can be left open for a logic 1 input, since they are internally pulled to the VAUX pin through 5kW resistors. Changing the VID inputs during operation is not recommended and could toggle the PGOOD signal and exercise the overvoltage protection. The output voltage program is Intel VRM8.5 compatible. FIGURE 8. OVERCURRENT OPERATION 0A 0V 2V 4V TIME T1 T2 T3 T0 T4 0V 10V FAULT REPORTED COUNT = 2 COUNT = 3 OVERLOAD APPLIED COUNT = 1 IPEAK = IOCSET ROCSET × rDS ON () ---------------------------------------------------- VSET FIGURE 9. OVERCURRENT DETECTION UGATE OCSET PHASE OC + - GATE CONTROL VCC 200 µA VDS iD ROCSET VIN = +5V OVERCURRENT TRIP: IOCSET + + PWM DRIVE VPHASE VIN VDS – = VOCSET VIN VSET – = iD rDS ON () × IOCSET ROCSET × > VDS VSET > |
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