6

FN9015.3

April 18, 2005

Functional Pin Descriptions

VCC (Pin 28)

Provide a 12V bias supply for the IC to this pin. This pin also

provides the gate bias charge for all the MOSFETs

controlled by the IC. The voltage at this pin is monitored for

Power-On Reset (POR) purposes.

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous

PWM converter’s lower MOSFET source to this pin.

VAUX (Pin 16)

Connect this pin to the ATX 3.3V output. The voltage present

at this pin is monitored for sequencing purposes. This pin

provides the necessary base bias for the NPN pass

transistors, as well as the current sunk through the 5kW VID

pull-up resistors.

SS13 (Pin 13)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 28mA current source, sets the soft-start

delayed by the time interval required by the charging of this

capacitor from 0V to 1.25V (see Soft-Start details).

SS24 (Pin 12)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 28mA current source, sets the

below 0.8V induces a chip reset (POR) and shutdown.

VTTPG (Pin 9)

VTTPG is an open collector output used to indicate the

threshold or when the SS13 pin is below 1.25V.

PGOOD (Pin 8)

PGOOD is an open collector output used to indicate the

status of the output voltages. This pin is pulled low when the

synchronous regulator output is not within ±10% of the

DACOUT reference voltage or when any of the other outputs

is below its undervoltage threshold.

VID3, VID2, VID1, VID0, VID25 (Pins 3-7)

VID3-25 are the TTL-compatible input pins to the 5-bit DAC.

The logic states of these five pins program the internal

voltage reference (DACOUT). The level of DACOUT sets the

well as the corresponding PGOOD and OVP thresholds.

Each VID pin is connected to the VAUX pin through a 5kW

pull-up resistor.

OCSET (Pin 23)

set the converter overcurrent (OC) trip point according to the

following equation:

An overcurrent trip cycles the soft-start function.

The voltage at OCSET pin is monitored for power-on reset

(POR) purposes.

PHASE (Pin 26)

Connect the PHASE pin to the PWM converter’s upper

MOSFET source. This pin represents the gate drive return

current path and is used to monitor the voltage drop across

the upper MOSFET for overcurrent protection.

UGATE (Pin 27)

Connect UGATE pin to the PWM converter’s upper

MOSFET gate. This pin provides the gate drive for the upper

MOSFET.

LGATE (Pin 25)

Connect LGATE to the synchronous PWM converter’s lower

MOSFET gate. This pin provides the gate drive for the lower

MOSFET.

COMP and FB (Pins 20, 21)

COMP and FB are the available external pins of the

synchronous PWM regulator error amplifier. The FB pin is

the inverting input of the error amplifier. Similarly, the COMP

pin is the error amplifier output. These pins are used to

compensate the voltage-mode control feedback loop of the

synchronous PWM converter.

VSEN1 (Pin 22)

This pin is connected to the synchronous PWM converters’

output voltage. The PGOOD and OVP comparator circuits

use this signal to report output voltage status.

DRIVE2 (Pin 1)

Connect this pin to the gate/base of a N-type external pass

transistor (MOSFET or bipolar). This pin provides the drive

for the 1.2V regulator’s pass transistor.

VSEN2 (Pin 11)

Connect this pin to the output of the standard buck PWM

regulator. The voltage at this pin is regulated to a 1.2V level.

This pin is also monitored for undervoltage events.

FIX (Pin 2)

Grounding this pin bypasses the internal resistor dividers that

set the output voltage of the 1.5V and 1.8V linear regulators.

This way, the output voltage of the two regulators can be

adjusted from 1.26V up to the input voltage (+3.3V or +5V;

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