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ISL6522ACR-T Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6522ACR-T Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 13 page 8 FN9122.2 April 13, 2005 Feedback Compensation Figure 7 highlights the voltage-mode control loop for a synchronous rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (error amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the ISL6522A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees . The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use these guidelines for locating the poles and zeros of the compensation network: Compensation Break Frequency Equations 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Figure 8 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual modulator gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The closed loop gain is constructed on the log-log graph of Figure 8 by adding the modulator gain (in dB) to the compensation gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES +12V ISL6522A SS GND VCC BOOT D1 LO CO VOUT Q1 Q2 PHASE +VIN CBOOT CVCC CSS FLC 1 2 π LO CO • • --------------------------------------- = FESR 1 2 π ESR CO • () • --------------------------------------------- = FZ1 1 2 π R • 2C1 • ---------------------------------- = FZ2 1 2 π R1 R3 + () C3 • • ------------------------------------------------------ = FP1 1 2 π R2 • C1 C2 • C1 C2 + ---------------------- • ------------------------------------------------------- = FP2 = 1 2 π R3 C3 • • ---------------------------------- FIGURE 7. VOLTAGE - MODE BUCK CONVERTER COMPENSATION DESIGN VOUT OSC REFERENCE LO CO ESR VIN ∆V OSC ERROR AMP PWM DRIVER (PARASITIC) - REF R1 R3 R2 C3 C2 C1 COMP VOUT FB ZFB ISL6522A ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN ZFB + ISL6522A |
Similar Part No. - ISL6522ACR-T |
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Similar Description - ISL6522ACR-T |
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