8

FN9122.2

April 13, 2005

Feedback Compensation

Figure 7 highlights the voltage-mode control loop for a

synchronous rectified buck converter. The output voltage

oscillator (OSC) triangular wave to provide a pulse-width

PHASE node. The PWM wave is smoothed by the output filter

The modulator transfer function is the small-signal transfer

peak-to-peak oscillator voltage

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

a closed loop transfer function with the highest 0dB crossing

180 degrees

. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 8. Use these guidelines for

locating the poles and zeros of the compensation network:

Compensation Break Frequency Equations

1. Pick Gain (R2/R1) for desired converter bandwidth

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual modulator gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 8. Using the above guidelines should give a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

amplifier. The closed loop gain is constructed on the log-log

graph of Figure 8 by adding the modulator gain (in dB) to the

compensation gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

The compensation gain uses external impedance networks

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

+12V

ISL6522A

SS

GND

VCC

BOOT

D1

Q1

Q2

PHASE

1

2

π

•

•

---------------------------------------

=

1

2

π

•

()

•

---------------------------------------------

=

1

2

π R

• 2C1

•

----------------------------------

=

1

2

π

R1 R3

+

() C3

•

•

------------------------------------------------------

=

1

2

π R2

•

C1 C2

•

C1 C2

+

----------------------





•

-------------------------------------------------------

=

1

2

π R3 C3

•

•

----------------------------------

FIGURE 7. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

OSC

REFERENCE

ESR

∆V

OSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

-

REF

R1

R3

R2

C3

C2

C1

COMP

FB

ISL6522A

COMPARATOR

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

+

-

+

-

+

ISL6522A