 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ISL6244CRZ-T Datasheet(PDF) 11 Page - Intersil Corporation |
|
||||||||||||||||||||||||||||||
ISL6244CRZ-T Datasheet(HTML) 11 Page - Intersil Corporation |
|
|
11 / 25 page  11 FN9106.3 December 28, 2004 PWM Operation The timing of each converter leg is set by the number of active channels. The default channel setting for the ISL6244 is four. One switching cycle is defined as the time between PWM1 pulse termination signals. The pulse termination signal is an internally generated clock signal which triggers the falling edge of PWM1. The cycle time of the pulse termination signal is the inverse of the switching frequency set by the resistor between the FS pin and ground. Each cycle begins when the clock signal commands the channel-1 PWM output to go low. The PWM1 transition signals the channel-1 MOSFET driver to turn off the channel-1 upper MOSFET and turn on the channel-1 synchronous MOSFET. In the default channel configuration, the PWM2 pulse terminates 1/4 of a cycle after PWM1. The PWM 3 output follows another 1/4 of a cycle after PWM2. PWM4 terminates another 1/4 of a cycle after PWM3. If PWM3 is connected to VCC, then two channel operation is selected and the PWM2 pulse terminates 1/2 of a cycle later. Connecting PWM4 to VCC selects three channel operation and the pulse-termination times are spaced in 1/3 cycle increments. Once a PWM signal transitions low, it is held low for a minimum of 1/4 cycle. This forced off time is required to ensure an accurate current sample. Current sensing is described in the next section. After the forced off time expires, the PWM output is enabled. The PWM output state is driven by the position of the error amplifier output signal, VCOMP, minus the current correction signal relative to the sawtooth ramp as illustrated in Figure 1. When the modified VCOMP voltage crosses the sawtooth ramp, the PWM output transitions high. The MOSFET driver detects the change in state of the PWM signal and turns off the synchronous MOSFET and turns on the upper MOSFET. The PWM signal will remain high until the pulse termination signal marks the beginning of the next cycle by triggering the PWM signal low. Current Sensing During the forced off time following a PWM transition low, the controller senses channel load current by sampling the voltage across the lower MOSFET rDS(ON), see Figure 15. A ground-referenced amplifier, internal to the ISL6244, connects to the PHASE node through a resistor, RISEN. The voltage across RISEN is equivalent to the voltage drop across the RDS(ON) of the lower MOSFET while it is conducting. The resulting current into the ISEN pin is proportional to the channel current, IL. The ISEN current is then sampled and held after sufficient settling time every switching cycle. The sampled current, In, is used for channel-current balance, load-line regulation and overcurrent protection. From Figure 15, the following equation for In is derived where IL is the channel current. If RDS(ON) sensing is not desired, an independent current- sense resistor in series with the lower MOSFET source can serve as a sense element. The circuitry shown in Figure 15 represents channel n of an N-channel converter. This circuitry is repeated for each channel in the converter, but may not be active depending upon the status of the PWM3 and PWM4 pins as described in the previous section. Channel-Current Balance The sampled current, In, from each active channel is used to gauge both overall load current and the relative channel current carried in each leg of the converter. The individual sample currents are summed and divided by the number of active channels. The resulting average current, IAVG, provides a measure of the total load current demand on the converter and the appropriate level of channel current. Using Figures 15 and 16, the average current is defined as: where N is the number of active channels and IOUT is the total load current. The average current is then subtracted from the individual channel sample currents. The resulting error current, IER, is then filtered before it adjusts VCOMP. The modified VCOMP signal is compared to a sawtooth ramp signal and produces a pulse width which corrects for any imbalance and drives the error current toward zero. Figure 16 illustrates Intersil’s patented current-balance method as implemented on channel-1 of a multi-phase converter. I n I L r DS ON () R ISEN ---------------------- = (EQ. 3) FIGURE 15. INTERNAL AND EXTERNAL CURRENT-SENSING CIRCUITRY In I SEN I L r DS ON () R ISEN -------------------------- = - + ISEN(n) RISEN SAMPLE & HOLD ISL6244 INTERNAL CIRCUIT EXTERNAL CIRCUIT VIN CHANNEL N UPPER MOSFET CHANNEL N LOWER MOSFET - + I L r DS ON () IL (EQ. 4) I AVG I 1 I 2 …I N ++ N ---------------------------------- = I AVG I OUT N ------------- r DS ON () R ISEN ---------------------- = ISL6244 |
Similar Part No. - ISL6244CRZ-T |
|
Similar Description - ISL6244CRZ-T |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
