11

Use a mix of input bypass capacitors to control the voltage

ripple across the MOSFETs. Use ceramic capacitors for the

high frequency decoupling and bulk capacitors to supply the

RMS current. Small ceramic capacitors can be placed very

close to the upper MOSFET to suppress the voltage induced

in the parasitic circuit impedances.

For board designs that allow through-hole components, the

temperature performance.

For surface mount designs, solid tantalum capacitors can be

used, but caution must be exercised with regard to the

capacitor surge current rating. These capacitors must be

capable of handling the surge-current at power-up. The TPS

series available from AVX is surge current tested.

+12V Boost Converter Inductor Selection

The inductor value is chosen to provide the required output

power to the load.

switching frequency, 100kHz.

Or, for L in uH, the maximum output current is nominally:

+12V Boost Converter Output Capacitor Selection

The total capacitance on the 12V output should be chosen

appropriately, so that the output voltage will be higher than

the undervoltage limit (9V) when the 5V Main soft-start time

has elapsed. This will avoid triggering of the 12V

undervoltage protection.

The maximum value of the boost capacitor, Comax that will

where L is the value of the boost inductor.

The output capacitor ESR and the boost inductor ripple

current determines the output voltage ripple. The ripple

voltage is given by:

and the maximum ripple current,

∆I

where L is the boost inductor calculated above, 5V is the

boost input voltage and 3.3

µ is the maximum on time for the

boost MOSFET.

MOSFET Considerations

The logic level MOSFETs are chosen for optimum efficiency

given the potentially wide input voltage range and output

power requirements. Two N-channel MOSFETs are used in

each of the synchronous-rectified buck converters for the

PWM1 and PWM2 outputs. These MOSFETs should be

and thermal management considerations.

The power dissipation includes two loss components;

conduction loss and switching loss. These losses are

distributed between the upper and lower MOSFETs

according to duty cycle (see the following equations). The

conduction losses are the main component of power

dissipation for the lower MOSFETs. Only the upper

MOSFET has significant switching losses, since the lower

device turns on and off into near zero voltage.

The equations assume linear voltage-current transitions and

do not model power loss due to the reverse-recovery of the

lower MOSFET’s body diode. The gate-charge losses are

dissipated by the ISL6235 and do not heat the MOSFETs.

However, a large gate-charge increases the switching time,

Ensure that both MOSFETs are within their maximum

junction temperature at high ambient temperature by

calculating the temperature rise according to package

thermal-resistance specifications.

5

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

3.3V AND 5V LOAD CURRENT

012345

3.3V

OUT-OF-PHASE

5V

IN-PHASE

INPUT CAPACITANCE RMS CURRENT AT VIN = 10.8V

FIGURE 4.

INPUT RMS CURRENT VS LOAD

Lmax

×

Ro

×

×

F

×

----------------------------------------------------------------

=

(EQ. 9)

Imax

13.88

LVo

×

-----------------

=

(EQ. 10)

Comax

Tss

L

---------- 0.115

µF

×

=

(EQ. 11)

V

RIPPLE

∆IL ESR

×

=

(EQ. 12)

∆IL

5V

L

------- 3.3

×µ

=

(EQ. 13)

P

UPPER

I

O

2

r

DS ON

()

×

V

OUT

×

V

IN

------------------------------------------------------------

I

O

V

IN

×

t

SW

×

F

S

×

2

----------------------------------------------------

+

=

P

LOWER

I

O

2

r

DS ON

()

×

V

IN

V

OUT

–

()

×

V

IN

---------------------------------------------------------------------------------

=

(EQ. 14)

ISL6235