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R1QPA4436RBG-30IA0 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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R1QPA4436RBG-30IA0 Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 31 page R1QPA4436RBG,R1QPA4418RBG Datasheet R10DS0147EJ0200 Rev.2.00 Page 9 of 30 Aug 01, 2014 Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation V DD SET-UP Cycle V DDQ V REF /DOFF K, /K Fix High (=Vddq) Power-up and Initialization Sequence VDD must be stable before K, /K clocks are applied. - Recommended voltage application sequence : VSS → VDD → VDDQ & VREF → VIN. (0 V to VDD, VDDQ < 200 ms) - Apply VREF after VDDQ or at the same time as VDDQ. - Then execute either one of the following sequences. 1. Single Clock Mode - Drive /DOFF high (/DOFF can be tied high from the start). - Then provide stable clocks (K, /K) for at least 20 us. 2. PLL Off Mode (/DOFF tied low) - In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us. PLL Constraints 1. These chips use the PLL. The clock input should have low phase jitter which is specified as tKC var. 2. The lower end of the frequency at which the PLL can operate is 250 MHz. (Please refer to AC Characteristics table for detail.) 3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again. |
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