R1QNA4436RBG-33IA0 datasheet(10/30 Pages) RENESAS

Part #	R1QNA4436RBG-33IA0

Description	144-Mbit QDR?줚I SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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10 / 30 page

R1QNA4436RBG,R1QNA4418RBG

Datasheet

R10DS0148EJ0200 Rev.2.00

Page 10 of 29

Aug 01, 2014

Programmable Output Impedance

1.

Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).

The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance

matching with a tolerance of 15% is between 175

Ω and 350 Ω. The total external capacitance of ZQ ball must be

less than 7.5 pF.

QVLD (Valid data indicator)

1.

QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q Valid

indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for

capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop capturing the data.

QVLD is edge aligned with CQ and /CQ.

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