13-10

Typical Applications

To maximize switching speed on the IH5140 family, TTL open

collector logic (15V with a 1k

Ω or less collector resistor)

and +10V. The SPDT and DPST switches are approximately

ration. 15V CMOS logic levels can be used (0V to +15V), but

propagation delays in the CMOS logic will slow down the

switching (typical 50ns

→ 100ns delays).

When driving the IH5140 Family from either +5V TTL or

CMOS logic, switching times run 20ns slower than if they

can be made as fast as the high level drive if

±5V strobe lev-

els are used instead of the usual 0V

→ +3.0V drive. Pin 13 is

taken to -5V instead of the usual GND and strobe input is

taken from +5V to -5V levels as shown in Figure 11.

The typical channel of the IH5140 family consists of both

P-Channel and N-channel MOSFETs. The N-channel

MOSFET uses a “Body Puller” FET to drive the body to -15V

(

±15V supplies) to get good breakdown voltages when the

switch is in the off state (see Figure 12). This “Body Puller”

FET also allows the N-Channel body to electrically float

when the switch is in the on state producing a fairly constant

Puller” FET improves switch performance, it can cause a

problem when analog input signals are present (negative

signals only) and power supplies are off. This fault condition

is shown in Figure 13.

Current will flow from -10V analog voltage through the drain

to body junction of Q1, then through the drain to body junc-

tion of Q3 to GND. This means that there is 10V across two

forward-biased silicon diodes and current will go to whatever

value the input signal source is capable of supplying. If the

analog input signal is derived from the same supplies as the

switch this fault condition cannot occur. Turning off the

supplies would turn off the analog signal at the same time.

This fault situation can also be eliminated by placing a diode

in series with the negative supply line (pin 14) as shown in

Figure 14. Now when the power supplies are off and a nega-

tive input signal is present this diode is reverse biased and

no current can flow.

ANALOG

OUT

ANALOG

OUT

ANALOG IN

(CHANNEL A)

ANALOG IN

(CHANNEL B)

-15V

-5V

+5V

+15V

-5V

+5V

CMOS

LEVEL

INPUT

STROBE

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

IH5141

FIGURE 11.

ANALOG IN

ANALOG OUT

D

Q2

±15V FROM

DRIVERS

D

Q1

G

S

B

G

S

G

Q3

S

B

-15V

“BODY PULLER” FET

±15V FROM

DRIVERS

D

SUBSTRATE

FIGURE 12.

ANALOG IN = -10V

Q2

GND WHEN POWER

SUPPLIES ARE OFF

N

Q1

N

P

Q3

SUBSTRATE

N

N

P

GND WHEN POWER

SUPPLIES ARE OFF

FIGURE 13.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

IH5141

-15V

+15V

+5V

1N914

OR EQUIVALENT

FIGURE 14.

IH5140 thru IH5145