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ICL7109IJL Datasheet(PDF) 8 Page - Intersil Corporation

Part # ICL7109IJL
Description  12-Bit, Microprocessor- Compatible A/D Converter
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ICL7109IJL Datasheet(HTML) 8 Page - Intersil Corporation

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Detailed Description
Analog Section
Figure 2 shows the equivalent circuit of the Analog Section
for the ICL7109. When the RUN/HOLD input is left open or
connected to V+, the circuit will perform conversions at a
rate determined by the clock frequency (8192 clock periods
per cycle). Each measurement cycle is divided into three
phases as shown in Figure 3. They are (1) auto-zero (A-Z),
(2) signal integrate (INT) and (3) de-integrate (DE).
Auto-Zero Phase
During auto-zero three things happen. First, input high and
low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Third, a feedback loop is
closed around the system to charge the auto-zero capacitor
CAZ to compensate for offset voltages in the buffer amplifier,
integrator, and comparator. Since the comparator is included
in the loop, the A-Z accuracy is limited only by the noise of
the system. In any case, the offset referred to the input is
less than 10
µV.
Signal Integrate Phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and low
are connected to the external pins. The converter then
integrates the differential voltage between IN HI and IN LO
for a fixed time. This differential voltage can be within a wide
common mode range of the inputs. At the end of this phase,
the polarity of the integrated signal is determined.
FIGURE 1B. TYPICAL CONNECTION DIAGRAM PARALLEL INTERFACE WITH 8048 MICROCOMPUTER
FIGURE 1.
9
25
26
40
39
/
5
20
5
6
17
26
19
18
40
1
2
V+
TEST
3 - 8
B9 - B12,
9 - 16
STATUS
HBEN
CE/LOAD
28
39
38
37
36
35
34
33
32
31
30
29
26
24
23
21
REF IN -
REF CAP-
REF CAP+
REF IN+
IN HI
IN LO
COMMON
INT
AZ
BUF
REF OUT
V-
RUN/HOLD
OSC SEL
OSC OUT
OSC IN
GND
GND
1
µF
0.01
µF
0.33
µF
0.15
µF
CAZ
CINT
RINT
1M
3.58MHz
CRYSTAL
-
+
+
INPUT
GND
EXTERNAL
REFERENCE
-5V
GND
-
20k
Ω 0.2V REF
200k
Ω 2V REF
+5V OR OPEN
GND
/
/
6
8
B1 - B8
1
4
7
8
11
20
XTAL1
TO
RESET
EA
WR
ALE
GND
28
30
29
27
10
XTAL2
P12
P11
P10
RD
P13
+5V
8
/
27
25
22
MODE
SEND
BUFF OSC OUT
+5V
+5V
SS
INT
2
RUN/HOLD
LBEN
POL,OR
12 - 19
DB0 - DB7
31 - 34
P14 - P17
35 - 38
P20 - P27
/
8
21 - 24
OTHER
I/O
GND
PSEN
GND
PROG
VDD
VCC
+5V
TL
+5V
+5V
+5V
ICL7109
8748/9048
3
+5V
ICL7109


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