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ADM487E Datasheet(PDF) 4 Page - Analog Devices |
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ADM487E Datasheet(HTML) 4 Page - Analog Devices |
4 / 16 page ADM485E/ADM487E/ADM1487E Rev. B | Page 4 of 16 TIMING SPECIFICATIONS VCC = 5 V ± 10%, TA = TMIN to TMAX, unless otherwise noted. Table 3. ADM485E/ADM1487E Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Driver Propagation Delay Input to Output, Low to High tDPLH 10 40 60 ns RDIFF = 54 Ω, CL1 = CL2 = 100 pF (see Figure 19 and Figure 20) Driver Propagation Delay Input to Output, High to Low tDPHL 10 40 60 ns RDIFF = 54 Ω, CL1 = CL2 = 100 pF (see Figure 19 and Figure 20) Output Skew to Output tSKEW 5 10 ns RDIFF = 54 Ω, CL1 = CL2 = 100 pF (see Figure 19 and Figure 20) Rise/Fall Time tDR, tDF 3 20 40 ns RDIFF = 54 Ω, CL1 = CL2 = 100 pF (see Figure 19 and Figure 20) Enable Time to High Level tDZH 45 70 ns CL = 100 pF, S1 closed (see Figure 21) Enable Time to Low Level tDZL 45 70 ns CL = 100 pF, S1 closed (see Figure 22) Disable Time from Low Level tDLZ 45 70 ns CL = 15 pF, S1 closed (see Figure 22) Disable Time from High Level tDHZ 45 70 ns CL = 15 pF, S1 closed (see Figure 21) RECEIVER Receiver Propagation Delay Input to Output, Low to High tRPLH 20 60 200 ns See Figure 23 and Figure 24 Receiver Propagation Delay Input to Output, High to Low tRPHL 20 60 200 ns See Figure 23 and Figure 24 |tPLH − tPHL| Differential Receiver Skew tSKEW 5 ns See Figure 23 and Figure 24 Enable Time to Low Level tRZL 25 50 ns CL = 15 pF, S2 closed (see Figure 25) Enable Time to High Level tRZH 20 50 ns CL = 15 pF, S1 closed (see Figure 25) Disable Time from Low Level tRLZ 20 50 ns CL = 15 pF, S2 closed (see Figure 25) Disable Time from High Level tRHZ 20 50 ns tPLH, tPHL < 50% of data period MAXIMUM DATA RATE fMAX 2.5 Mbps |
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