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5962F9563501V9A Datasheet(PDF) 10 Page - Intersil Corporation |
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5962F9563501V9A Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 36 page  10 HS-RTX2010RH Operation Control of all data paths and the Program Counter Register, ( ), is provided by the Instruction Decoder. This hardware determines what function is to be performed by looking at the contents of the Instruction Register, ( ), and subsequently determines the sequence of operations through data path control. Instructions which do not perform memory accesses execute in a single clock cycle while the next instruction is being fetched. As shown in Figure 10, the instruction is latched into at the beginning of a clock cycle. The instruction is then decoded by the processor. All necessary internal operations are performed simultaneously with fetching the next instruction. Instructions which access memory require two clock cycles to be executed. During the first cycle of a memory access instruction, the instruction is decoded, the address of the memory location to be accessed is placed on the Memory Address Bus (MA19-MA01), and the memory data (MD15-MD00), is read or written. During the second cycle, ALU operations are performed, the address of the next instruction to be executed is placed on the Memory Address Bus, and the next instruction is fetched, as indicated in the bottom half of Figure 10. BYTE SWAP HS-RTX2010RH OFF-CHIP USER INTERFACES TIMER/COUNTERS TP0 TP1 TP2 TC0 TC1 TC2 ALU YT PC I TOP CR MD SR CONTROL STACK IMR IVR IBC CONTROL INTERRUPT CONTROL PAGE MEMORY CLOCK AND CONTROL RESET INTERFACE MEMORY BUS INTERFACE ASIC BUS DPR IPR UPR CPR UBR SPR SUR SVR -1 +1 INSTRUCTION DECODER IR LEADING ZERO DETECTOR BARREL SHIFTER 16 x 16 MAC MXR MHR MLR 256 x 21 RETURN MEMORY STACK 256 x 16 PARAMETER MEMORY STACK NEXT NOTE: contains the 5 most significant bits (20-16) of the top element of the Return Stack. FIGURE 9. HS-RTX2010RH FUNCTIONAL BLOCK DIAGRAM IPR PC IR IR HS-RTX2010RH |
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