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HS8-RTX2010RH Datasheet(PDF) 4 Page - Intersil Corporation |
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HS8-RTX2010RH Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 36 page 4 47 L6 MA11 Output; Address Bus 48 L8 MA12 Output; Address Bus 49 K8 MA13 Output; Address Bus 50 L9 VDD Power 51 L10 MA14 Output; Address Bus 52 K9 MA15 Output; Address Bus 53 L11 MA16 Output; Address Bus 54 K10 MA17 Output; Address Bus 55 J10 MA18 Output; Address Bus 56 K11 MA19 Output; Address Bus 57 J11 GND Ground 58 H10 LDS Output 59 H11 UDS Output 60 F10 NEW Output 61 G10 BOOT Output 62 G11 PCLK Output 63 G9 MR/W Output 64 F9 MD00 I/O; Data Bus 65 F11 MD01 I/O; Data Bus PGA And CQFP Pin/Signal Assignments (Continued) CQFP PGA PIN SIGNAL NAME TYPE 66 E11 MD02 I/O; Data Bus 67 E10 MD03 I/O; Data Bus 68 E9 MD04 I/O; Data Bus 69 D11 GND Ground 70 D10 MD05 I/O; Data Bus 71 C11 MD06 I/O; Data Bus 72 B11 MD07 I/O; Data Bus 73 C10 VDD Power 74 A11 MD08 I/O; Data Bus 75 B10 MD09 I/O; Data Bus 76 B9 MD10 I/O; Data Bus 77 A10 MD11 I/O; Data Bus 78 A9 MD12 I/O; Data Bus 79 B8 MD13 I/O; Data Bus 80 A8 MD14 I/O; Data Bus 81 B6 GND Ground 82 B7 MD15 I/O; Data Bus 83 A7 GA00 Output; Address Bus 84 C7 GA01 Output; Address Bus - C3 - Isolated Alignment Pin PGA And CQFP Pin/Signal Assignments (Continued) CQFP PGA PIN SIGNAL NAME TYPE Output Signal Descriptions SIGNAL CQFP RESET LEVEL DESCRIPTION OUTPUTS NEW 60 1 NEW: A HIGH on this pin indicates that an Instruction Fetch is in progress. BOOT 61 1 BOOT: A HIGH on this pin indicates that Boot Memory is being accessed. This pin can be set or reset by accessing bit 3 of the Configuration Register. MR/W 63 1 MEMORY READ/WRITE: A LOW on this pin indicates that a Memory Write operation is in progress. UDS 59 1 UPPER DATA SELECT: A HIGH on this pin indicates that the high byte of memory (MD15-MD08) is being accessed. LDS 58 1 LOWER DATA SELECT: A HIGH on this pin indicates that the low byte of memory (MD07-MD00) is being accessed. GIO 16 1 ASIC I/O: A LOW on this pin indicates that an ASIC Bus operation is in progress. GR/W 15 1 ASIC READ/WRITE: A LOW on this pin indicates that an ASIC Bus Write operation is in progress. PCLK 62 0 PROCESSOR CLOCK: Runs at half the frequency of ICLK. All processor cycles begin on the rising edge of PCLK. Held low extra cycles when WAIT is asserted. TCLK 2 0 TIMING CLOCK: Same frequency and phase as PCLK but continues running during Wait cycles. INTA 3 0 INTERRUPT ACKNOWLEDGE: A HIGH on this pin indicates that an Interrupt Acknowledge cycle is in progress. Input Signal, Bus, and Power Connection Descriptions SIGNAL CQFP LEAD DESCRIPTION INPUTS WAIT 13 WAIT: A HIGH on this pin causes PCLK to be held LOW and the current cycle to be extended. ICLK 14 INPUT CLOCK: Internally divided by 2 to generate all on-chip timing (CMOS input levels). RESET 12 A HIGH level on this pin resets the RTX. Must be held high for at least 4 rising edges of ICLK plus 12 ICLK cycle setup and hold times. HS-RTX2010RH |
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