4

HS-80C85RH

FIGURE 1. POWER-ON RESET CIRCUIT

INTR

10

I

Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to

the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program

Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a

RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR

is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is

accepted.

INTA

11

O

Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruc-

tion cycle after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some

other interrupt port.

RST 5.5

RST 6.5

RST 7.5

9

8

7

I

Restart Interrupts: These three inputs have the same timing as INTR except they cause an

internal RESTART to be automatically inserted.

The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher

priority than INTR. In addition, they may be individually masked out using the SIM instruction.

TRAP

6

I

Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as

INTR or RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority

of any interrupt. (See Table 6.)

RESET IN

36

I

Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops.

The data and address buses and the control lines are 3-stated during RESET and because of

the asynchronous nature of RESET the processor’s internal registers and flags may be altered

by RESET with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connec-

tion to an R-C network for power-on RESET delay (see Figure 1). Upon power-up, RESET IN

must remain low for at least 10 “clock cycle” after minimum VDD has been reached. For proper

reset operation after the power-up duration, RESET IN should be kept low a minimum of three

clock periods. The CPU is held in the reset condition as long as RESET IN is applied.

RESET OUT

3

O

Reset Out: Reset Out indicates cpu is being reset. Can be used as a system reset. The signal

is synchronized to the processor clock and lasts an integral number of clock periods.

X1

X2

1

2

I

O

X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator.

X, can also be an external clock Input from a logic gate. The input frequency is divided by 2 to

give the processor’s internal operating frequency.

CLK

37

O

Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input

period.

SID

5

I

Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM

instruction is executed.

SOD

4

O

Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.

VCC

40

I

Power: +5V supply.

GND

20

I

Ground: Reference.

SYMBOL

PIN

NUMBER

TYPE

DESCRIPTION

R1

VDD

RESET IN

C1

TYPICAL POWER-ON RESET RC VALUES

†

R1 = 75K

Ω

C1 = 1

µF

Spec Number

518054