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HS-1410RH Datasheet(PDF) 2 Page - Intersil Corporation |
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HS-1410RH Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 2 page 2 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Die Characteristics DIE DIMENSIONS: 59 mils x 59 mils x 19 mils ±1 mil (1500 µm x 1500µm x 483µm ± 25.4µm) INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 4k Å ±0.5kÅ Top Metallization: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8k Å ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16k Å ±0.8kÅ Substrate: UHF-1, Bonded Wafer, DI ASSEMBLY RELATED INFORMATION: Substrate Potential (Powered Up): Floating (Recommend Connection to V-) ADDITIONAL INFORMATION: Transistor Count: 75 Metallization Mask Layout HS-1410RH NOTE: This pad is not bonded out on packaged units. Die users may set a GND reference, via this pad, to ensure the TTL compatibility of the DIS input when using asymmetrical supplies (e.g. V+ = 10V, V- = 0V). V- OPTIONAL GND (NOTE) OUT +IN -IN V+ DISABLE HS-1410RH |
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