6-102

Functional Diagram

NOTES:

1. Select Latch: L Low

→ Q = D and Q latches on rising edge of L.

2. Address Latches And Gated Decoders: Latch on falling edge of E and gate on falling edge of E.

3. All lines positive logic-active high.

4. Three-State Buffers: A high

→ output active.

5. Data Latches: L High

→ Q = D and Q latches on falling edge of L.

GATED

ROW

DECODER

A0

32

5

5

A

A1

A5

A6

A7

A

LATCHED

ADDRESS

REGISTER

32 x 32

MATRIX

D

33

A

A

S1

S2

W

E

LATCH

SELECT

A4

A3

A2

LATCHED ADDRESS

REGISTER

LATCHES

DATA

OUTPUT

GATED COLUMN

DECODER

AND DATA I/O

D0

A

A

A

A

A

A

A

A

L

8

8

8

8

D

D

D

D1

D2

D3

DQ

L

Q

Q

Q

Q

Q0

Q1

Q2

Q3

HM-6551/883