6

In this write cycle G has control of the output after a period,

TGHQZ. G switching the output to a high impedance state

allows data in to be applied without bus contention after

Low Voltage Data Retention

Intersil CMOS RAMs are designed with battery backup in

mind. Data retention voltage and supply current are guaran-

teed over temperature. The following rules ensure data

retention:

1. Chip Enable (E) must be held high during data retention;

2. On RAMs which have selects or output enables (e.g., S,

G), one of the selects or output enables should be held in

the deselected state to keep the RAM outputs high im-

pedance, minimizing power dissipation.

3. Inputs which are to be held high (e.g., E) must be kept be-

and down transitions.

the minimum operating voltage (4.5V).

(17) TDVWH

(21) TDVEH

(18) TWHDX

(15)

TGHQZ

ADDRESS

G

E

W

Q

D

(10) TAVAX

(22) TAVWH

(14)

TWHAX

(11) TELWH

(12) TAVWL

FIGURE 3. WRITE CYCLE II

(13) TWLWH

4.5V

E

4.5V

>55ns

DATA

RETENTION

TIMING

FIGURE 4. DATA RETENTION TIMING

HM-65162