6-5

Timing Waveforms

The address information is latched in the on-chip registers

on the falling edge of E (T = 0), minimum address setup and

hold time requirements must be met. After the required hold

time, the addresses may change state without affecting

device operation. During time (T = 1), the outputs become

enabled but data is not valid until time (T = 2), W must

remain high throughout the read cycle. After the data has

been read, E may return high (T = 3). This will force the out-

put buffers into a high impedance mode at time (T = 4). G is

used to disable the output buffers when in a logical “1” state

(T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for

the next cycle.

HIGH

NEXT

(11)

TAVEL

(12)

TELAX

ADD

(5)

TEHQZ

VALID DATA OUT

(5)

TEHQZ

(8)

TGHQZ

(7)

TGLQX

A

E

W

DQ

G

TIME

REFERENCE

-1

01

2

3

4

5

TAVQV

(2)

(11)

TAVEL

(18)

TELEL

(9)

TELEH

(10)

TEHEL

(10)

TEHEL

TELQV

(1)

TELQX

(3)

TGLQV

(6)

FIGURE 1. READ CYCLE

VALID ADD

(11)

TAVEL

(12)

TELAX

(11)

TAVEL

(17)

TWHDX

HIGH

VALID DATA IN

A

E

W

DQ

G

TIME

REFERENCE

-1

01

2

3

4

5

VALID ADD

NEXT ADD

(18)

TELEL

(10)

TEHEL

(10)

TEHEL

(9)

TELEH

(13)

TWLWH

(14)

TWLEH

(16)

TDVWH

FIGURE 2. WRITE CYCLE

(15)

TELWH

HM-6516