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HM-6514 Datasheet(PDF) 4 Page - Intersil Corporation |
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HM-6514 Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 7 page 6-4 AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6514S-9, HM-6514B-9, HM-6514-9) TA = -55 oC to +125oC (HM-6514B-8, HM-6514-8) SYMBOL PARAMETER LIMITS UNITS TEST CONDITIONS HM-6514S-9 HM-6514B-9 HM-6514-9 MIN MAX MIN MAX MIN MAX (1) TELQV Chip Enable Access Time - 120 - 220 - 300 ns (Notes 1, 3) (2) TAVQV Address Access Time - 120 - 220 - 320 ns (Notes 1, 3, 4) (3) TELQX Chip Enable Output Enable Time 5 - 5 - 5 - ns (Notes 2, 3) (4) TEHQZ Chip Enable Output Disable Time - 50 - 80 - 100 ns (Notes 2, 3) (5) TELEH Chip Enable Pulse Negative Width 120 - 200 - 300 - ns (Notes 1, 3) (6) TEHEL Chip Enable Pulse Positive Width 50 - 90 - 120 - ns (Notes 1, 3) (7) TAVEL Address Setup Time 0 - 20 - 20 - ns (Notes 1, 3) (8) TELAX Address Hold Time 40 - 50 - 50 - ns (Notes 1, 3) (9) TWLWH Write Enable Pulse Width 120 - 200 - 300 - ns (Notes 1, 3) (10) TWLEH Chip Enable Write Pulse Setup Time 120 - 200 - 300 - ns (Notes 1, 3) (11) TELWH Chip Enable Write Pulse Hold Time 120 - 200 - 300 - ns (Notes 1, 3) (12) TDVWH Data Setup Time 50 - 120 - 200 - ns (Notes 1, 3) (13) TWHDX Data Hold Time 0 - 0 - 0 - ns (Notes 1, 3) (14) TWLDV Write Data Delay Time 70 - 80 - 100 - ns (Notes 1, 3) (15) TWLEL Early Output High-Z Time 0 - 0 - 0 - ns (Notes 1, 3) (16) TEHWH Late Output High-Z Time 0 - 0 - 0 - ns (Notes 1, 3) (17) TELEL Read or Write Cycle Time 170 - 290 - 420 - - (Notes 1, 3) NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL. HM-6514 |
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