6-74

In the HM-6508/883 Read Cycle, the address information is

latched into the on-chip registers on the falling edge of E

(T = 0). Minimum address setup and hold time requirements

must be met. After the required hold time, the addresses

may change state without affecting device operation. During

time (T = 1) the data output becomes enabled; however, the

data is not valid until during time (T = 2).

W must remain high for the read cycle. After the output data

has been read, E may return high (T = 3). This will disable

the chip and force the output buffer to a high impedance

state. After the required E high time (TEHEL) the RAM is

ready for the next memory cycle (T = 4).

TRUTH TABLE

TIME REFERENCE

INPUTS

OUTPUTS

FUNCTION

E

WA

D

Q

-1

H

X

X

X

Z

Memory Disabled

0

H

V

X

Z

Cycle Begins, Addresses are Latched

1

L

H

X

X

X

Output Enabled

2

L

H

X

X

V

Output Valid

3

H

X

X

V

Read Accomplished

4

H

X

X

X

Z

Prepare for Next Cycle (Same as -1)

5

H

V

X

Z

Cycle Ends, Next Cycle Begins (Same as 0)

TIME

REFERENCE

(8) TAVEL

TELAX

(9)

(8) TAVEL

NEXT

TELEL

TEHEL

(15)

(7)

TELEH

(6)

(7)

TEHEL

TWLEH

(14)

(12)

TWLWH

(13)

VALID DATA INPUT

TELWH

TWHDX (11)

TDVWH

(10)

HIGH 2

-1

01

2

3

4

5

A

E

W

D

O

VALID

FIGURE 2. WRITE CYCLE

HM-6508/883