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HIP6304CB Datasheet(PDF) 11 Page - Intersil Corporation |
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HIP6304CB Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 14 page 11 Example: Using the previously given conditions, and For ILT = 50A, n= 2 Then ISAMPLE = 25.49A As discussed previously, the voltage drop across each Q2 transistor at the point in time when current is sampled is rDSON (Q2) x ISAMPLE. The voltage at Q2’s drain, the PHASE node, is applied through the RISEN resistor to the HIP6304 ISEN pin. This pin is held at virtual ground, so the current into ISEN is: ISENSE = ISAMPLE x rDS(ON) (Q2) / RISEN. RIsen = ISAMPLE x rDS(ON) (Q2) / 50µA Example: From the previous conditions, where ILT = 50A, ISAMPLE = 25.49A, rDS(ON) (Q2) = 4m Ω Then: RISEN = 2.04K and ICURRENT TRIP = 165% Short circuit ILT = 82.5A. Channel Frequency Oscillator The channel oscillator frequency is set by placing a resistor, RT, to ground from the FS/DIS pin. Figure 10 is a curve showing the relationship between frequency, FSW, and resistor RT. To avoid pickup by the FS/DIS pin, it is important to place this resistor next to the pin. If this pin is also used to disable the converter, it is also important to locate the pull- down device next to this pin. Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. These voltage spikes can degrade efficiency, radiate noise into the circuit and lead to device over-voltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff transition of the upper PWM MOSFET. Prior to turnoff, the upper MOSFET was carrying channel current. During the turnoff, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. Contact Intersil for evaluation board drawings of the component placement and printed circuit board. There are two sets of critical components in a DC-DC converter using a HIP6304 controller and a HIP6601 gate driver. The power components are the most critical because they switch large amounts of energy. Next are small signal components that connect to sensitive nodes or supply critical bypassing current and signal coupling. The power components should be placed first. Locate the input capacitors close to the power switches. Minimize the length of the connections between the input capacitors, CIN, and the power switches. Locate the output inductors and output capacitors between the MOSFETs and the load. Locate the gate driver close to the MOSFETs. The critical small components include the bypass capacitors for VCC and PVCC on the gate driver ICs. Locate the bypass capacitor, CBP, for the HIP6304 controller close to the device. It is especially important to locate the resistors associated with the input to the amplifiers close to their respective pins, since they represent the input to feedback amplifiers. Resistor RT, that sets the oscillator frequency should also be located next to the associated pin. It is especially important to place the RSEN resistor(s) at the respective terminals of the HIP6304. A multi-layer printed circuit board is recommended. Figure 11 shows the connections of the critical components for one output channel of the converter. Note that capacitors CIN and COUT could each represent numerous physical capacitors. Dedicate one solid layer, usually the middle layer of the PC board, for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. Keep the metal runs from the PHASE terminal to inductor LO1 short. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for 50 100 10 20 200 500 1,000 5,000 10,000 2,000 1 2 5 10 20 50 100 200 500 1,000 CHANNEL OSCILLATOR FREQUENCY, FSW (kHz) FIGURE 10. RESISTANCE RT vs FREQUENCY HIP6304 |
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