2-291

The modulator transfer function is the small-signal transfer

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

closed loop transfer function with high 0dB crossing frequency

degrees

. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 11. Use these guidelines for

locating the poles and zeros of the compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

Compensation Break Frequency Equations

Figure 12 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown in Figure 12. Using the above guidelines

should yield a Compensation Gain similar to the curve plotted.

The open loop error amplifier gain bounds the compensation

of the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 12 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the compensation

transfer function and plotting the gain.

The compensation gain uses external impedance networks

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than

45 degrees. Include worst case component variations when

determining phase margin.

PWM2 Controller Feedback Compensation

To reduce the number of external small-signal components

required by a typical application, the standard PWM

controller is internally stabilized. The only stability criteria

that needs to be met relates the minimum value of the output

inductor to the equivalent ESR of the output capacitor bank,

as shown in the following equation:

FIGURE 8. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

OSC

REFERENCE

ESR

OSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

+

-

DACOUT

R1

R3

R2

C3

C2

C1

COMP

FB

HIP6020

COMP

DRIVER

DETAILED COMPENSATION COMPONENTS

PHASE

+

-

+

-

F

LC

1

2

π

L

O

C

O

×

×

----------------------------------------

=

F

ESR

1

2

π ESR C

O

×

×

-----------------------------------------

=

F

Z1

1

2

π R

× 2C1

×

-----------------------------------

=

F

Z2

1

2

π

R1

R3

+

() C3

×

×

-------------------------------------------------------

=

F

P1

1

2

π R

2

C1

C2

×

C1

C2

+

----------------------





×

×

-------------------------------------------------------

=

F

P2

1

2

π R

× 3C3

×

-----------------------------------

=

100

80

60

40

20

0

-20

-40

-60

10M

1M

100K

10K

1K

100

10

OPEN LOOP

ERROR AMP GAIN

COMPENSATION

FREQUENCY (Hz)

GAIN

MODULATOR

GAIN

FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP

GAIN

20

V

IN

V

PP

–

------------------







log

20

R2

R1

--------





log

L

OUT MIN

()

ESR

OUT

10

1.75

×

2

π

×

BW

×

------------------------------------------------

=

HIP6020