2-262

The modulator transfer function is the small-signal transfer

gain and the output filter, with a double pole break frequency

oscillator voltage,

Modulator Break Frequency Equations

The compensation network consists of the error amplifier

provide a closed loop transfer function with an acceptable

Phase margin is the difference between the closed loop

the compensation network’s poles, zeros and gain to the

components (R1, R2, R3, C1, C2, and C3) in Figure 11.

Use these guidelines for locating the poles and zeros of the

compensation network:

1. Pick Gain (R2/R1) for desired converter bandwidth.

6. Check Gain against Error Amplifier’s Open-Loop Gain.

7. Estimate Phase Margin - repeat if necessary.

Compensation Break Frequency Equations

Figure 12 shows an asymptotic plot of the DC-DC

converter’s gain vs frequency. The actual modulator gain has

which is not shown in Figure 12. Using the above guidelines

should yield a compensation gain similar to the curve

plotted. The open loop error amplifier gain bounds the

with the capabilities of the error amplifier. The closed loop

gain is constructed on the log-log graph of Figure 12 by

adding the modulator gain (in dB) to the compensation gain

(in dB). This is equivalent to multiplying the modulator

transfer function to the compensation transfer function and

plotting the gain.

The compensation gain uses external impedance networks

stable control loop has a 0dB gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

Oscillator Synchronization

The PWM controllers use a triangle wave for comparison with

the error amplifier output to provide a pulse-width modulated

wave. Should the output voltages of the two PWM converters

be programmed close to each other, then cross-talk could

cause nonuniform PHASE pulse-widths and increased output

voltage ripple. The HIP6019 avoids this problem by

synchronizing the two converters 180

° out-of-phase for DAC

FIGURE 11. VOLTAGE-MODE BUCK CONVERTER COMPEN-

SATION DESIGN

OSC

REFERENCE

ESR

OSC

ERROR

AMP

PWM

DRIVER

(PARASITIC)

+

-

REFERENCE

R1

R3

R2

C3

C2

C1

COMP

FB

HIP6019

COMP

DRIVER

DETAILED FEEDBACK COMPENSATION

PHASE

+

-

+

-

F

LC

1

2

π

L

O

C

O

×

×

----------------------------------------

=

F

ESR

1

2

π ESR C

O

×

×

-----------------------------------------

=

F

Z1

1

2

π R

× 2C1

×

-----------------------------------

=

F

Z2

1

2

π

R1

R3

+

() C3

×

×

-------------------------------------------------------

=

F

P1

1

2

π R

2

C1

C2

×

C1

C2

+

----------------------





×

×

-------------------------------------------------------

=

F

P2

1

2

π R

× 3C3

×

-----------------------------------

=

100

80

60

40

20

0

-20

-40

-60

10M

1M

100K

10K

1K

100

10

OPEN LOOP

ERROR AMP GAIN

20LOG

COMPENSATION

FREQUENCY (Hz)

GAIN

20LOG

MODULATOR

GAIN

FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP

GAIN

HIP6019