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HIP1012CB Datasheet(PDF) 6 Page - Intersil Corporation |
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HIP1012CB Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 15 page 6 The HIP1012 responds to a load short (defined as a current level 3X the OC set point) immediately, driving the relevant N-Channel MOSFET gate to 0V in less than 1 µs. The gate voltage is then slowly ramped up turning on the N-Channel MOSFET to the programmed current limit level, this is the start of the time out period. The programmed current level is held until either the OC event passes or the time out period expires. If the former is the case then the N-Channel MOSFET is fully enhanced and the CTIM charging current is diverted away from the capacitor. If the time out period expires prior to OC resolution then both gates are quickly pulled to 0V turning off both N-Channel MOSFETs simultaneously. Upon any OC or UV condition the PGOOD signal will pull low when tied high through a resistor to the logic supply. This pin is a fault indicator but not the OC latch off indicator. For an OC latch off indication, monitor CTIM, pin 10. This pin will rise rapidly to 12V once the time out period expires. See block diagram for OC latch off circuit suggestion. The HIP1012 is reset by a rising edge on either PWRON pin and is turned on by either PWRON pin being driven low. The HIP1012 can control either +12V/5V or +3.3V/+5V supplies. Tying the PWRON1 pin to VDD, invokes the +3.3V/+5V voltage mode. In this mode, the external charge pump capacitor is not needed and Cpump, pin 11 is also tied directly to VDD. HIP1012 Application Considerations For Applications where voltage tolerances are of critical concern the HIP1012A is better suited as it has a minimum nominal OC Vth performance of 50mV verses 100mV with the HIP1012 over the entire temperature range. This allows the use of lower Rsense value resistors resulting in higher efficiency. When using the HIP1012 in the 12V and 5V mode additional VDD decoupling may be necessary to prevent a power on reset due to a sag on VDD pin upon an OC latch off. The addition of a capacitor from VDD to GND may often be adequate but a small value isolation resistor may also be necessary. See the Simplified Schematic. Current loop stabilization is facilitated through a small value resistor in series with the gate timing capacitor. As the HIP1012 drives a highly inductive current load, instability characterized by the gate voltage repeatedly ramping up and down may appear. A simple method to enhance stability is provided by the substitution of a larger value gate resistor. Typically this situation can be avoided by eliminating long point to point wiring to the load. Random resets may occur if the HIP1012 sense pins are pulled below ground when turning off a highly inductive load. Place a large load capacitor (10-50 µF) on the output to eliminate the unintended resets. During the Time Out delay period with the HIP1012 in current limit mode, the VGS of the external N-Channel MOSFETs is reduced driving the N-Channel MOSFET switch into a high rDS(ON) state. Thus avoid extended time out periods as the external N-Channel MOSFETs may be damaged or destroyed due to excessive internal power dissipation. Refer to the MOSFET manufacturers data sheet for SOA information. With the high levels of inrush current e.g., highly capacitive loads and motor start up currents, choosing the current limiting level is crucial to provide both protection and still allow for this inrush current without latching off. Consider this in addition to the time out delay when choosing MOSFETs for your design. Physical layout of Rsense resistors is critical to avoid the possibility of false over current occurrences. Ideally trace routing between the Rsense resistors and the HIP1012 is direct and as short as possible with zero current in the sense lines. Refer to the demo boards for examples. External Pull Down resistors (5k Ω) from the xISEN pins to ground will prevent the outputs from floating when the external switch FETs are disabled and the outputs are open. TABLE 1. RILIM RESISTOR NOMINAL OC VTH 15k Ω 150mV 10k Ω 100mV 7.5k Ω 75mV 4.99k Ω 50mV NOTE: Nominal OC Vth = Rilim x 10 µA. TABLE 2. CTIM CAPACITOR NOMINAL TIME OUT PERIOD 0.022 µF 4.4ms 0.047 µF 9.4ms 0.1 µF 20ms NOTE: Nominal time-out period in seconds = CTIM x 200kΩ. HIP1012, HIP1012A |
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