Electronic Components Datasheet Search |
|
HIP0060AB Datasheet(PDF) 4 Page - Intersil Corporation |
|
HIP0060AB Datasheet(HTML) 4 Page - Intersil Corporation |
4 / 7 page 4 Serial Diagnostic Link A serial diagnostic link via the SPI bus provides the means to clock fault data in and out of the fault register to the micro- controller. When the microcontroller receives an INT inter- rupt signal, data is clocked from the Serial Diagnostic Register to determine what fault bit has been set. Appropri- ate action for the fault may then be taken, as defined by the programming of the microcontroller. Serial Diagnostic Register Fault bits consist of one OT bit and one OL bit for each switching channel (A, B, C and D). Data is transferred out of SO MSB first on the rising edge of SCK after CS goes low. Data is shifted into the input shift register on the falling edge of SCK. The defined order of the DO0 to DO7 fault bits is as follows: HIP0060 devices may be linked in cascade for the purposes of SPI control. Serial data is clocked in and out of each HIP0060 and then back to the host microcontroller. All linked devices have a common control sequence. When CS goes low, fault data is shifted to the Serial Diagnostic Register. SCK must be low when CS goes low. Also, when CS goes low, SO changes from a three-state to a low state and remains low until SCK goes high. Serial data is transferred by SCK. After the serial data is transferred, SCK must remain low as CS goes high. The serial data transfer must be a continuous sequence while CS is low. Serial Peripheral Interface The Serial Peripheral Interface (SPI) bus is system con- trolled by a host micro. The SPI bus controls the Serial Diag- nostic Link with the CS (Chip Select), SCK, SI, SO and RST (Reset) lines. Figures 4 and 5 define the timing and protocol for the bus. Reset Operation The RST input is an active low reset input. When RST is low, the internal diagnostic flags are cleared but not the shift reg- ister. When RST is low, all outputs and output switches are disabled. To clear the shift register, CS is switched from high to low during or after a reset while there are no active faults, jamming data from the cleared fault flags into the shift regis- tor. The RST input has an internal pull-up to sustain a logic high when floating. The VDD input is the power supply to the 5V logic and the POR function. When the VDD is less than the VDD(POR) threshold, the output drivers are shutoff. To insure that the diagnostic link shift register is correct after VDD is less than VDD(POR), a manual reset must be executed. BIT NAME CONDITION REQUIRED TO SET BIT DO0 OTA OT in Output Driver A, TJ ≥ TLIM DO1 OTB OT in Output Driver B, TJ ≥ TLIM DO2 OTC OT in Output Driver C, TJ ≥ TLIM DO3 OTD OT in Output Driver D, TJ ≥ TLIM DO4 OLA OL in Output Driver A, OFF Load > ROLD DO5 OLB OL in Output Driver B, OFF Load > ROLD DO6 OLC OL in Output Driver C, OFF Load > ROLD DO7 OLD OL in Output Driver D, OFF Load > ROLD FIGURE 1. TYPICAL HIP0060 APPLICATION AS A LOW SIDE SWITCH FOR INDUCTIVE LOADS, LAMPS AND SMALL LINEAR MOTORS OR STEPPER MOTORS OUTA OUTB RELAY SOLENOID VDD +5V HIP0060 INA INC RST 4.7k Ω INT IND INB VBATT OUTC OUTD LAMP MOTOR VBATT M HIP0060 |
Similar Part No. - HIP0060AB |
|
Similar Description - HIP0060AB |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |