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HI7188EVAL Datasheet(PDF) 5 Page - Intersil Corporation |
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HI7188EVAL Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 22 page 7-1851 Pin Descriptions 40 LEAD PDIP 44 LEAD MQFP PIN NAME PIN DESCRIPTION 1 41 MODE Mode input. Used to select between Synchronous Self Clocking (MODE = 1) or Synchronous Ex- ternal Clocking (MODE = 0) for the Serial Port. 2 42 SCLK Serial interface clock. Synchronizes serial data transfers. Data is input on the rising edge and out- put on the falling edge. 3 43 SDO Serial Data Out. Serial data is read from this line when using a 3-wire serial protocol such as the Motorola Serial Peripheral Interface. 4 44 SDIO Serial Data IN or OUT. This line is bidirectional programmable and interfaces directly to the Intel Standard Serial Interface using a 2-wire serial protocol. 5 1 OSC1 Oscillator clock input for the device. A crystal connected between OSC1 and OSC2 will provide a clock to the device, or an external oscillator can drive OSC1. The oscillator frequency should be 3.6864MHz to maintain Line Noise Rejection. 6 2 OSC2 Used to connect a crystal source between OSC1 and OSC2. Leave open otherwise. 7 3, 30 DVDD Positive Digital supply (+5V). 8, 31 4, 29, 39 DGND Digital supply ground. 9, 30 5, 6, 27, 28 AVSS Negative analog power supply (-5V). 10 7 VINL1 Analog input low for Channel 1. 11 8 VINH1 Analog input high for Channel 1. 12 9 VINL2 Analog input low for Channel 2. 13 10 VINH2 Analog input high for Channel 2. 14 11 VINL3 Analog input low for Channel 3. 15 12 VINH3 Analog input high for Channel 3. 16 13 VINL4 Analog input low for Channel 4. 17 14 VINH4 Analog input high for Channel 4. 18 15 VINL5 Analog input low for Channel 5. 19 16 VINH5 Analog input high for Channel 5. 20 17 VINL6 Analog input low for Channel 6. 21 18 VINH6 Analog input high for Channel 6. 22 19 VINL7 Analog input low for Channel 7. 23 20 VINH7 Analog input high for Channel 7. 24 21 VINL8 Analog input low for Channel 8. 25 22 VINH8 Analog input high for Channel 8. 26 23 VCM Common mode voltage. Must be tied to the mid point of AVDD and AVSS. 27 24 VRLO External reference input. Should be negative referenced to VRHI. 28 25 VRHI External reference input. Should be positive referenced to VRLO. 29 26 AVDD Positive analog power supply (+5V). 32 31 RST Active low Reset pin. Used to initialize modulator, filter, RAMs, registers and state machines. 33 32 CA Calibration active output. Indicates that at least one active channel is in a calibration mode. 34 33 MXC Multiplexer control output. Indicates that the conversion for the active channel is complete. 35 34 A0 Logical channel count output (LSB). 36 35 A1 Logical channel count output. 37 36 A2 Logical channel count output (MSB). 38 37 EOS End of scan output. Signals the end of a channel scan (all active channels have been converted) and data is available to be read. Remains low until data RAM is read. 39 38 RSTI/O I/O reset (active low) input. Resets serial interface state machine only. 40 40 CS Active low chip select pin. Used to select a serial data transfer cycle. When high the SDO and SDIO pins are three-state. HI7188 |
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