6

The second function is a “lamp test”. When TEST is pulled

high (to V+) all segments will be turned on and the display

should read “1888”. The TEST pin will sink about 15mA

under these conditions.

CAUTION: In the lamp test mode, the segments have a constant DC

voltage (no square-wave). This may burn the LCD display if main-

tained for extended periods.

Digital Section

Figures 6 shows the digital section for the HI7106. In the

HI7106, an internal digital ground is generated from a 6V

Zener diode and a large P-Channel source follower.

This supply is made stiff to absorb the relative large capaci-

tive currents when the back plane (BP) voltage is switched.

The BP frequency is the clock frequency divided by 800. For

three readings/sec., this is a 60Hz square wave with a nomi-

nal amplitude of 5V. The segments are driven at the same

frequency and amplitude and are in phase with BP when

OFF, but out of phase when ON. In all cases negligible DC

voltage exists across the segments.

The polarity indication is “on” for negative analog inputs. If

IN LO and IN HI are reversed, this indication can be

reversed also, if desired.

HI7106

V+

BP

TEST

21

37

TO LCD

BACKPLANE

TO LCD

DECIMAL

POINT

1M

Ω

FIGURE 4. SIMPLE INVERTER FOR FIXED DECIMAL POINT

HI7106

V+

BP

TEST

DECIMAL

POINT

SELECT

CD4030

GND

V+

TO LCD

DECIMAL

POINTS

FIGURE 5. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE

7

SEGMENT

DECODE

SEGMENT

OUTPUT

0.5mA

2mA

INTERNAL DIGITAL GROUND

TYPICAL SEGMENT OUTPUT

V+

LCD PHASE DRIVER

LATCH

7

SEGMENT

DECODE

LOGIC CONTROL

INTERNAL

7

SEGMENT

DECODE

1000’s

100’s

10’s

1’s

TO SWITCH DRIVERS

FROM COMPARATOR OUTPUT

DIGITAL

GROUND

CLOCK

40

39

38

OSC 1

OSC 2

OSC 3

BACKPLANE

21

V+

TEST

V-

500

Ω

37

26

6.2V

COUNTER

COUNTER

COUNTER

COUNTER

1

c

a

b

c

d

f

g

e

a

b

a

b

c

d

f

g

e

a

b

c

d

f

g

e

†

ONE INVERTER SHOWN FOR CLARITY

FIGURE 6. HI7106 DIGITAL SECTION

HI7106